Initial SME Support - SE-122 by FinnWilkinson · Pull Request #248 · UoB-HPC/SimEng

FinnWilkinson · 2022-09-15T12:30:40Z

Within this PR is the background support needed to support the Armv9.2-a SME extension. Below gives an overview of the changes made :

Added Config file options Streaming-Vector-Length and MatrixRow-Count
Added SME instruction groups to the AArch64/InstructionGroups.hh file
Added the ZA matrix register to the AArch64 register files
Added decode logic for SME instructions
- This includes a function to allocate a sub-tile its correct rows
Added the SVCR system register to keep track of Streaming SVE Mode and ZA-Enabled Modes
Implemented some initial instructions (without helper functions)
- AArch64_FMOPA_MPPZZ_S Perform an outer-produce accumulate operation on two 32-bit vectors
- AArch64_LD1_MXIPXX_H_S Load a horizontal slice of a 32-bit ZA tile
- AArch64_LD1_MXIPXX_V_S Load a vertical slice of a 32-bit ZA tile
- AArch64_ST1_MXIPXX_H_S Store a horizontal slice of a 32-bit ZA tile
- AArch64_ST1_MXIPXX_V_S Store a vertical slice of a 32-bit ZA tile
- AArch64_ZERO_M Zero out given sub-tiles of / whole ZA register
- AArch64_MSRpstatesvcrImm1 Update the SVCR register; used by aliases SMSTART and SMSTOP
Added tests for each new instruction
Implemented new SME related test suite helper functions
Added 5 new exception types to ensure the core is in the correct context mode for SME execution

Other non-SME changes include:

Updated the test suite to be compatible with LLVM 14.0.5
- Test suite still works for previous versions of LLVM used (i.e. 12.0.0)
Set the default LLVM version in CMakeLists.txt to LLVM 14.0.5
Optimised source and destination operand arrays in AArch64-Instruction
- Due to implementation of SME, the old arrays (4 total) would be initialised to 260 Register Values / Registers as standard
- This caused a large slow down, and so the arrays have been replaced with vectors to mitigate this performance regression
Added dedicated zero register to the architectural register file to reduce decode logic
Removed Un-used functions in AArch64-Instruction
Implemented a Copy Constructor for Instruction objects
- This is typically defined implicitly, however, as two member variables are references the Copy Constructor needs defining explicitly
Fixed Jenkins pipeline building scripts to actually use the targeted compiler at all stages of the build/linking process
Updated the Capstone repo used to UoB-HPC's fork at the next branch

…ency, rather than update the VCT register to total cycles completed.

…m register (PMCCNTR_EL0 for Aarch64).

A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.

…ow for a wider param space (#229)

Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.

…e Linux machines.

A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.

…246)

…ts (#235)

* Moved counter timer logic from main into Architecture, allowing the implementation to be architecture agnostic. * Added test for CNTVCT register. * Updated sveGetPattern auxiliary function to work for any instruction string. * Ensured all necessary SVE instructions included pattern recognition. * Changed specialFiles generation directory to be the build location. * Fixed AArch64_LD1RQ_D_IMM's invalid increments of its index variable. * Improved conditional branch not taken target and remove loop closing direction due to emergent bug. * Resolved LSQ bugs for comparisons against the total req limit and forwarding operands from flushed loads. * Updated comment in sveGetPattern Aux function.

This pull request updates SimEng to use the Armv9.2-update branch of the UoB-HPC Capstone Fork. Changes to the CMake files have been changed to reflect build changes in the upstream Capstone:next branch. A pre-upstreamed update to Capstone has been merged into the Armv9.2-update, which adds support for the AArch64 Armv9.2-a ISA (including SVE2 and SME instructions). As such, minor fixes have been made to accommodate changes to instruction enums, aliasing logic, and other changes.

This PR has reduced the number of unused copies of the memory image and thus reduced the memory requirements of a SimEng simulation. The process memory image is instantiated once through malloc/remalloc calls and shared between simulation objects through shared pointers.

This PR introduces a new CoreInstance class. The class supports the creation of a SimEng core model, storing all the relevant simulation objects within shared pointers. A key factor in this change being introduced was to improve the ease SimEng's interactions with other frameworks e.g. SST.

This PR adds prefixes to all SimEng outputs to help distinguish between simulated workload outputs and the outputs from the framework.

This PR moves the dispatch rate restriction from dispatch unit wide to the individual reservation stations. This improves the parameterization of the unit as a whole.

…:next.

FinnWilkinson · 2022-10-25T11:38:02Z

Missing SME docs at the moment. Will add ASAP

jj16791

A few comments and clarification needed

…ded docs.

jj16791

One small comment

jj16791

All looks good to me

rahahahat · 2022-10-27T10:55:10Z

All looks good to me.

dANW34V3R

One possible major issue, other minor comments

jj16791

The updates look good to me. Good job!

rahahahat

New changes, look good to me

dANW34V3R

All looks good to me

This PR adds functionality into SimEng to support the AArch64 SME extension. 6 new SME instructions have been implemented, along with the SVCR Streaming-SVE-Mode context switching functionality. Additionally, the default LLVM version has been updated to 14.0.5 in order to support the SME regression tests. The AArch64 Instruction class now has a copy constructor, optimising the use of cached instructions. Updated Jenkin's pipeline scripts to work with LLVM 14 Changes the Capstone usage to fix an existing memory leak, as mentioned in Issue #261.

FinnWilkinson added the enhancement New feature or request label Sep 15, 2022

FinnWilkinson requested review from dANW34V3R, jj16791 and rahahahat September 15, 2022 12:30

FinnWilkinson self-assigned this Sep 15, 2022

FinnWilkinson commented Sep 27, 2022

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Comment thread src/lib/arch/aarch64/Instruction_execute.cc

FinnWilkinson changed the title ~~Initial SME Support~~ SE-122 Initial SME Support Sep 27, 2022

FinnWilkinson mentioned this pull request Oct 10, 2022

Enable support for CoreInstance to assemble and execute string instructions via LLVM - SE-145 #253

Closed

FinnWilkinson changed the title ~~SE-122 Initial SME Support~~ Initial SME Support - SE-122 Oct 11, 2022

FinnWilkinson and others added 19 commits October 17, 2022 17:08

Updated the Virtual Counter Timer logic to iterate at the Timer-Frequ…

4638d44

…ency, rather than update the VCT register to total cycles completed.

Implemented functionality to update the Processor Cycle Counter syste…

1c22a63

…m register (PMCCNTR_EL0 for Aarch64).

Missing sys reg handling (#228)

1ba50c3

A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.

Updated some config options to be read as uint16_t not uint8_t to all…

dbdb09a

…ow for a wider param space (#229)

Removed prefix from standard types such as due to build errors on som…

46660b5

…e Linux machines.

Updated jenkins armclang build script to use new armclang22 compiler (#…

1d4d091

…246)

Prevent ExceptionHandler processing if there are active memory reques…

19c05cb

…ts (#235)

Added comments explaining ELF File structure in Elf.cc file. (#242)

5761757

Additional aarch64 and syscall support (#233)

e62ad85

Initial M1 Firestorm core model (#245)

ce3620b

Output prefix (#249)

a9460a7

This PR adds prefixes to all SimEng outputs to help distinguish between simulated workload outputs and the outputs from the framework.

Dispatch rate SE-146 (#251)

cb6b5da

This PR moves the dispatch rate restriction from dispatch unit wide to the individual reservation stations. This improves the parameterization of the unit as a whole.

Documentation updates for release v0.9.4 SE-155 (#254)

260a203

jj16791 force-pushed the dev branch from b2c619f to 260a203 Compare October 17, 2022 16:10

Updated CMake files to compile SimEng with latest version of Capstone…

db512bc

…:next.

FinnWilkinson commented Oct 24, 2022

View reviewed changes

Resolved outstanding PR comments.

364bfae

rahahahat reviewed Oct 25, 2022

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Comment thread src/include/simeng/arch/aarch64/helpers/sve.hh

Comment thread src/include/simeng/arch/aarch64/helpers/sve.hh

Comment thread src/lib/ModelConfig.cc

Comment thread src/lib/arch/aarch64/Instruction_address.cc

Comment thread src/lib/arch/aarch64/Instruction_address.cc

Added SME documentation.

8fc1876

jj16791 requested changes Oct 26, 2022

View reviewed changes

FinnWilkinson added 4 commits October 26, 2022 17:09

Changes based on PR review comments.

ee3799f

Reverted zero-reg operand logic.

ad5ce01

Updated ExceptionResult->uop comment to reflect actual usage.

d66b652

Updated an exception's uop scoreboard releasing functionality & ammen…

197e3ca

…ded docs.

jj16791 requested changes Oct 27, 2022

View reviewed changes

Comment thread src/lib/models/outoforder/Core.cc Outdated

Corrected processExceptionHandler function in OoO core.

51f045d

jj16791 approved these changes Oct 27, 2022

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rahahahat approved these changes Oct 28, 2022

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dANW34V3R requested changes Oct 28, 2022

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FinnWilkinson added 2 commits October 31, 2022 13:01

Altered SVCR functionality to ensure functional correctness.

1a82e24

Minor changes made inline with PR comments.

38d8c7f

FinnWilkinson requested review from dANW34V3R, jj16791 and rahahahat October 31, 2022 13:21

jj16791 approved these changes Oct 31, 2022

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rahahahat approved these changes Oct 31, 2022

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FinnWilkinson mentioned this pull request Nov 1, 2022

Architecture::predecode leaks memory for every core tick #261

Closed

dANW34V3R approved these changes Nov 1, 2022

View reviewed changes

FinnWilkinson linked an issue Nov 1, 2022 that may be closed by this pull request

Architecture::predecode leaks memory for every core tick #261

Closed

FinnWilkinson merged commit 4165d09 into dev Nov 1, 2022

FinnWilkinson deleted the SME-PR branch June 8, 2023 10:06

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