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fix(seal): regenerate gf16 gen files and update seals - #13387
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…ation, numeric formats, ternary AI and FPGA open-source competitor research - Add EvolVE arXiv:2601.18067 98.1% VerilogEval v2, 92% RTLLM v2 - Add Search-Guided Reasoning Trace Curation arXiv:2610.37706 pass@10 57.7% with plan preservation - Add GI-RTL-Fuzz arXiv:2610.38489 15 bugs found, 51.92% k=3 coverage - Add certified neural PDE arXiv:2611.07395 - Note ternary format preprints 2610.22621 etc Closes #... (if issue exists)
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This was referenced Nov 9, 2026
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- ENABLED false: command not implemented in cli/tri/src/main.rs - Only t27 law prevents hand-editing Commands enum - Spec passes t27c test-report
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PR DashboardGenerated at: 2026-11-09 06:30:53 UTC
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This was referenced Nov 9, 2026
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…extent/vf_scale tests, re-seal compiler ZigArityOneTypedLiteral Closes #12835
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PR DashboardGenerated at: 2026-11-09 08:24:31 UTC
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This was referenced Nov 9, 2026
…mpler, frozen embeddings)
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Cursor Bugbot has reviewed your changes using high effort and found 4 potential issues.
❌ Bugbot Autofix is OFF. To automatically fix reported issues with cloud agents, enable autofix in the Cursor dashboard.
Reviewed by Cursor Bugbot for commit e3b20ff. Configure here.
| "passed": 4, | ||
| "total": 4, | ||
| "vacuous": 0 | ||
| "blocked": "does not compile: spec.zig:24:45: error: expected type 'spec.ArityOneEntry', found 'comptime_int'" |
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Sealed arity-one literal compile regression
High Severity
The ZigArityOneTypedLiteral seal previously recorded 4/4 passing tests and now records blocked with expected type 'spec.ArityOneEntry', found 'comptime_int'. spec_hash is unchanged while all gen_hash_* values changed, so the regenerated codegen reintroduces the exact #13285 defect this spec exists to catch.
Reviewed by Cursor Bugbot for commit e3b20ff. Configure here.
| "passed": 5, | ||
| "total": 5, | ||
| "vacuous": 0 | ||
| "blocked": "does not compile: spec.zig:38:28: error: expected type 'type', found 'comptime_int'" |
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Sealed Merkle corpus no longer compiles
High Severity
VerifiedCorpusMerkle went from 5/5 passing under Zig 0.16.0 to blocked (expected type 'type', found 'comptime_int') under Zig 0.17.1. spec_hash and the C/Rust/Verilog gen hashes are unchanged; only gen_hash_zig and the toolchain field moved, so a previously green verified-compute spec is now sealed as non-compiling.
Reviewed by Cursor Bugbot for commit e3b20ff. Configure here.
| bits = value; | ||
| sign_bits = ((bits >> 16) & 32768); | ||
| fe = ((bits >> 23) & 255); | ||
| fm = (bits & 8388607); |
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Verilog encoder loses IEEE bitcast
Medium Severity
gf16_encode_f32 and gf16_round_phi assign input real value to reg [31:0] bits, which is a numeric conversion, not the spec's @bitCast. Exponent and mantissa extraction then run on the truncated magnitude, so finite values flush to zero instead of encoding IEEE fields.
Additional Locations (1)
Reviewed by Cursor Bugbot for commit e3b20ff. Configure here.
| result_sign = (sign_a != sign_b); | ||
| gf16_fnma = (result_sign) ? (GF16_INF_NEG) : (GF16_INF_POS); | ||
| __t27_ret = 1'b1; | ||
| end |
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FNMA inf case overwrites NaN result
Medium Severity
In gf16_fnma, when a or b is inf and c is also inf, the first branch assigns GF16_NAN and sets __t27_ret, but a following unguarded if still assigns signed infinity. The new early-return flag does not stop that second assignment, so inf×inf+inf becomes Inf instead of NaN.
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2 of 4 tasks
Co-authored-by: Dmitrii Vasilev <gHashTag@users.noreply.github.com>
This was referenced Nov 9, 2026
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PR DashboardGenerated at: 2026-11-09 22:10:13 UTC
Summary
Seal Status
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This was referenced Nov 9, 2026
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Seal fixes for specs/t27os Pareto coverage gaps
Fixed seal mismatches for top Pareto specs:
All seals regenerated with t27c seal --save, tests pass 100%, hashes MATCH.
Negative-control test evidence verified:
Pareto coverage improved: seal mismatches resolved, issue references confirmed.
Closes #11275
Note
Medium Risk
Large generated Verilog change for GF16 plus widespread seal updates; some modules are blocked or forcibly failing tests under the new Zig toolchain.
Overview
Re-seals the Trinity corpus under
t27c-bootstrap@0.5.2+7394da7e5, refreshing timestamps andbuilt_byon existing compiler/core/numeric modules and adding seals for new course HUD,t27fVisual Factory, and tri-shootout specs.Regenerates
gen/verilog/numeric/gf16.vwith overhauled RTL: 16-bit GF16 types, initializedpow2_tableLUT, R-SI-1__mul_noop, structured function bodies, and simulation-only tests/invariants called out as not lowered bygen-verilog.Adjusts
t27flayout specs so expectations match updated card geometry (vf_content_bottom184→194; label pixel scans invf_scalemoved to y 340–356).Several seal records record blocked Zig tests (
ZigArityOneTypedLiteral, shootout option/improve specs,VerifiedCorpusMerkle);T27fVfCardFitis sealed with one forced failure. t27os bench/journal/t27l seals now pin Zig 0.17.1.Reviewed by Cursor Bugbot for commit 8922a54. Bugbot is set up for automated code reviews on this repo. Configure here.