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…ency, rather than update the VCT register to total cycles completed.
…m register (PMCCNTR_EL0 for Aarch64).
A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.
…ow for a wider param space (#229)
Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.
…e Linux machines.
A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.
* Moved counter timer logic from main into Architecture, allowing the implementation to be architecture agnostic. * Added test for CNTVCT register. * Updated sveGetPattern auxiliary function to work for any instruction string. * Ensured all necessary SVE instructions included pattern recognition. * Changed specialFiles generation directory to be the build location. * Fixed AArch64_LD1RQ_D_IMM's invalid increments of its index variable. * Improved conditional branch not taken target and remove loop closing direction due to emergent bug. * Resolved LSQ bugs for comparisons against the total req limit and forwarding operands from flushed loads. * Updated comment in sveGetPattern Aux function.
This pull request updates SimEng to use the Armv9.2-update branch of the UoB-HPC Capstone Fork. Changes to the CMake files have been changed to reflect build changes in the upstream Capstone:next branch. A pre-upstreamed update to Capstone has been merged into the Armv9.2-update, which adds support for the AArch64 Armv9.2-a ISA (including SVE2 and SME instructions). As such, minor fixes have been made to accommodate changes to instruction enums, aliasing logic, and other changes.
This PR has reduced the number of unused copies of the memory image and thus reduced the memory requirements of a SimEng simulation. The process memory image is instantiated once through malloc/remalloc calls and shared between simulation objects through shared pointers.
This PR introduces a new CoreInstance class. The class supports the creation of a SimEng core model, storing all the relevant simulation objects within shared pointers. A key factor in this change being introduced was to improve the ease SimEng's interactions with other frameworks e.g. SST.
This PR adds prefixes to all SimEng outputs to help distinguish between simulated workload outputs and the outputs from the framework.
… cmake. (#231) This PR implements the `SST` wrapper and `simeng::MemoryInterface` needed for successful integration with SST. It also adds support for conditional compilation through `CMake`.
…ency, rather than update the VCT register to total cycles completed.
…m register (PMCCNTR_EL0 for Aarch64).
A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.
…ow for a wider param space (#229)
Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.
…e Linux machines.
A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.
dANW34V3R
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General structure is still looking good. A short PR description needed, you could use the one from #250.
Main points are; the need for the binaries and the need for all of the conditional compilation. I have left comments for both of these.
FinnWilkinson
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Nov 8, 2022
…teCore and added comments in Assemble.cc
FinnWilkinson
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dANW34V3R
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Nov 8, 2022
dANW34V3R
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Nice work. Removal of most of the ifdefs makes the code much more readable
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Adds Integration with SST and a custom framework for testing SST
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Adds Integration with SST and a custom framework for testing SST
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This PR implements the SST wrapper needed for successful integration with SST. It also adds support for conditional compilation through CMake and a custom testing framework used for testing the integration. Documentation for running and building SimEng with the SST integration enabled is temporarily available here. It will be added to the source at a later stage.
The custom SST testing framework exposes two main testing macros (TEST_GROUP and TEST_CASE) along with multiple evaluation macros. The framework runs sst with a config file specified by the TEST_GROUP and captures the stdout of the child process, injecting it to individual test cases and allowing the user to define multiple checks on that captured output through the use of evaluation macros. The testing framework also exposes a parser, which parses the output of the sst simulation and turns the output into structs, which can then be used by the tests. Currently, there are two formats:
The entire output is parsed into:
This format is parsed, and
<text>is extracted by the parser.The testing framework adds 2 new compile definitions to the initial CMake configuration command:
-DSIMENG_ENABLE_SST_TESTS: This definition enables SST Tests only if -DSIMENG_ENABLE_TESTS is defined.-DSST_TESTS_MODEL_CONFIG_PATH: This definition is optional; using this compile definition, the user can specify a SimEng model config. However, if not provided. All tests will, by default, use a64fx-sst.yaml model configuration.There are 2 sst configuration files added in the testing framework: fastL1ForBinaries.py and fastL1withParams_config.py.
Arguments can be passed to these sst configuration files via test cases using a key value format, i.e. key=value.
Currently, 6 argument types can be passed by test cases and are replaced in the configuration files, ultimately to be passed to SimEngCoreWrapper:
execBin: This is the path to an executable executed by SSTSimEng. Example: execBin=/ab/cd/exec.args: These are all the args passed to the executable. Example: args=10 20 50.withSrc: This signals if the test will pass a string of instructions to be assembled by LLVM. Example: withSrc=<True|False>.source: This contains all instructions to be assembled by LLVM. Example: source=mov x1, #0.heap: This contains comma-separated values, which will be used to initialise the heap. Example: heap=10,20,30.clw: This contains the cache line width in bytes: Example: clw=64.