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[Tracking] DeepSeek-v4 HybridModel merge plan - #5795

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@hxbai hxbai commented Jul 14, 2026 •

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DeepSeek-V4 main tracker

Updated: 2026-10-20. Tracks mainline support for the DSv4 HybridModel performance recipe.

Progress: Core foundations and all three tracked functional ports—Hash MoE, packed THD/CP, and mHC PP/VPP—are merged into main. Remaining work is performance parity.

BatchedLinear blocker: Dev #5722 and main #7971 both depend on TE #3160 for the optimized path. In #7971, the pinned TE does not provide BatchedLinear: the draft uses the einsum fallback and skips real BatchedLinear tests. Resolve the TE dependency, update the pin, recheck the final API, and pass BF16/MXFP8 GPU validation before marking the optimization ready. #7971 remains a draft.

Finished — merged into main

Completed features and supporting infrastructure
PR title and summary Dev PR(s) Main PR(s)
DSv4 native/fused attention and HybridModel integration #4458, #4894, #6349, #5762 #6400, #6402, #6404, #6405
Native/fused mHC and HybridModel/MTP integration #2943, #3828, #4624, #6172 #4531, #6401
CSA parameter precision and FP8-context isolation #5308 #6400, #5929
Selective-FP32 runtime and optimizer lifecycle #6124 #5929, #4547
Clamped SwiGLU across expert paths #4481, #5130 #5940
Safe MLA RoPE and packed-position handling #5018, #5526 #5944
Variable-length data, packing, and CP-layout foundations #2924 #5902, #5903, #5908, #6625, #6684, #6734, #6742, #6776, #6912
THD variable-token dispatcher support #2924, #5048 #5008
Muon FP8 parameter gather and buffer reuse #5470 #6754
TE graph parameter-gradient clone removal — (main-first) #5893
NCCL EP baseline — (main-first) #5129
NCCL EP zero-copy, overflow handling, and MXFP8 dispatch — (main-first) #5735, #6229, #6524, #7195
Device-initiated GroupedLinear #6847 #6000
Local CUDA graph memory-pool reuse — (main-first) #5451
Local CUDA graph stream-aliasing fix — (main-first) #6643
DSv4 packed THD/CP — Static context parallelism and MTP support. #5011, #5087, #5691, #5706, #5809 #7469
Hash MoE — Routing and training integration. #4481, #5130, #4596, #6704 #6403
mHC PP/VPP — Pipeline support for multistream residuals. #2943, #4518, #5471 #7336

Existing main PRs — performance work

PR title and summary Dev PR(s) Main PR(s)
MoK backend — Dispatch, expert execution, combine, and shared-output gate; single-node GB200 functional validation passed. #6572, #7289, #7391 #8210 (ready for review)
BatchedLinear output projection — Optimized path blocked on TE #3160. #5722 (open) #7971 (draft)
DSv4 FLOPs accounting — Correct reported metrics; no execution speedup. #5142, #5358, #5762 #7972 (ready for review)
THD TE attention graphs — Scheduler-packed capture/replay; replaces #5783. #4359, #5724 #8361 (ready for review)
mHC TE wrappers and MTP discovery — Base graph support; recompute split remains below. #4190, #7014, #6583 #7337 (draft)
Remove dummy attention masks — Reduce graph memory. #5131 #5173 (open)
Muon compact layout + FP8 sync — Reduce optimizer layout memory. #5388, #5470 #5479 (open)
Output inverse RoPE reconstruction — Reduce saved activation memory. #7036 #8399 (draft)
DP-balanced all-gather rerouting — Reduce transport-buffer memory. #6378 #7047 (open; includes this item)

MoK dependency installation #7696 is merged. #8210 is the tracked backend port onto current main.

Remaining performance ports — dev merged

PR title and summary Dev PR(s) Main PR(s)
Compact BF16/MXFP8 indexer — Faster CSA scoring and Top-K. #5992 —
Fused compressor pooling — Faster pooling forward/backward. #5984, #7064 —
THD/CP preprocessing kernels — Fused layout and sparse-loss preprocessing. #7064 — (#7469 provides functional THD/CP support)
mHC recompute + attention graph split — Preserve recompute memory savings with graphs. #5841, #6661, #7385 — (#7337 covers base graphs only)
MTP halo prefetch and counter batching — Reduce MTP communication overhead. #6246 — (#7469 provides basic rolls)
CP compressor projection before compaction — Avoid retaining compact hidden-size inputs. #7388 —
Fixed-shape packed PP, including VPP — Skip repeated shape exchange. #7000, #7483 —

The CC 10.7 mapping in dev #7779 is merged. Carry it with the CuTe layout-kernel port; current main does not contain the module it patches.

— = no active main PR identified that covers the remaining optimization. These are feature gaps, not a required one-PR-per-row split. Existing PRs and partial coverage are listed above; detailed code comparisons and validation evidence are kept locally.

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FDecaYed added a commit to FDecaYed/Megatron-LM that referenced this pull request Jul 21, 2026
Add configurable boundary-fill semantics and roll packed THD MTP inputs across contiguous context-parallel shards without crossing sequence boundaries.

Reconstructed from the MTP portion of NVIDIA#5795 on top of the padded-cu-seqlens fix in NVIDIA#4495.

Signed-off-by: Deyu Fu <Deyu.Foo@gmail.com>
FDecaYed added a commit to FDecaYed/Megatron-LM that referenced this pull request Jul 21, 2026
Add the unfused compressed sparse attention algorithm, inert configuration fields, and focused algorithm coverage without enabling a model variant.

Reconstructed from NVIDIA#4458 and its corrections as part of the frozen feature set in NVIDIA#5795.

Signed-off-by: Deyu Fu <Deyu.Foo@gmail.com>
FDecaYed added a commit to FDecaYed/Megatron-LM that referenced this pull request Jul 21, 2026
Enable SBHD-only DSv4 Hybrid attention orchestration, model-variant validation, backend-explicit specs, and MTP layer-ratio plumbing.

Reconstructed from NVIDIA#4458, NVIDIA#4518, NVIDIA#5018, and NVIDIA#5526 as part of the frozen feature set in NVIDIA#5795.

Signed-off-by: Deyu Fu <Deyu.Foo@gmail.com>
FDecaYed added a commit to FDecaYed/Megatron-LM that referenced this pull request Jul 21, 2026
Map the canonical padded vocabulary size into TransformerConfig for hash routing and hide the redundant generated CLI field.

Reconstructed from NVIDIA#4481 and the frozen feature set in NVIDIA#5795.

Signed-off-by: Deyu Fu <Deyu.Foo@gmail.com>
Replace the historical aggregate with the frozen HybridModel-only feature oracle used to define the reviewable prerequisite and DSv4 slices. Exclude GPTModel support, dynamic context parallelism, SFT-specific packing, optimizer-state offload, and full-iteration CUDA graphs. Align the HybridEP padding flag with the current NVIDIA#5008 contract.

Signed-off-by: Deyu Fu <deyuf@nvidia.com>
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FDecaYed force-pushed the codex/dsv4-main-port branch from 9596ade to 234919d Compare July 23, 2026 15:53
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@FDecaYed FDecaYed changed the title [main] DeepSeek-v4 full support on main [Tracking] DeepSeek-v4 HybridModel merge plan Jul 23, 2026
@sbhavani sbhavani mentioned this pull request Oct 7, 2026
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