All pull requests

Pull requests

• [compiler] Elide reduction mask for specialized extents

  CLA Signed
  #3910·coder-2011 opened Oct 11, 2026Contributor·

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• [backend] Promote cute and pallas backends to stable

  CLA Signed
  #3909·oulgen opened Oct 11, 2026Contributor·

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• [autotuner] Batch rows per program for small-N reductions

  CLA Signed
  #3907·coder-2011 opened Oct 11, 2026Contributor·

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• [compiler] Balance dispatch across root loops

  CLA Signed
  #3906·ZenAlexa opened Oct 11, 2026·

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  2

• [autotuner] Fuse looped reductions that share an operand

  CLA Signed
  #3905·coder-2011 opened Oct 11, 2026Contributor·

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• [cutedsl] Keep dead lane loops that carry an accumulator

  CLA Signed
  #3903·jansel opened Oct 11, 2026Contributor·

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• [epilogue_subtile] Fix stores split along the wrong dimension

  CLA Signed
  #3896·yashb98 opened Oct 10, 2026Contributor·

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• [compiler] Add hl.device_scope() as sugar for dummy grid(1) loop

  CLA Signed
  #3869·hinriksnaer opened Oct 10, 2026Collaborator·

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• Switch Intel Triton kernel build format to zebin

  CLA Signed
  #3861·NaOHCC opened Oct 9, 2026Contributor·

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• [pretuned] Add GB300 output-only attention recipes

  CLA Signed
  #3856·yushangdi opened Oct 8, 2026Contributor·

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• [autotune] Fix precompile capabilities and diagnostics

  CLA Signed
  #3852·yushangdi opened Oct 8, 2026Contributor·

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• [CuTe] Support zero-dimensional tensor loads and stores

  CLA Signed
  #3821·yushangdi opened Oct 7, 2026Contributor·

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• Codex/cute topk only

  CLA Signed
  #3819·yushangdi opened Oct 7, 2026Contributor·

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• Codex/pipeline autotune

  CLA Signed
  #3811·yushangdi opened Oct 7, 2026Contributor·

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• Set V.graph during inductor masked value analysis (#3809)

  CLA Signedmeta-exported
  #3809·njriasan opened Oct 6, 2026Contributor·

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• [autotune] Detect automatic autotune handoff points

  CLA Signed
  #3806·yushangdi opened Oct 6, 2026Contributor·

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• [Not For Commit] Helion TPU attention results

  CLA Signed
  #3802·AmesingFlank opened Oct 5, 2026Contributor·

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• [metal] Support lane-strided threadgroup reductions via serial fold

  CLA Signed
  #3801·aditvenk opened Oct 5, 2026Contributor·

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• [metal] Support fp32-accumulate/fp16-output MPP matmul via scalar store

  CLA Signed
  #3800·aditvenk opened Oct 5, 2026Contributor·

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• Drop the Triton third-party cache, which never hits

  CLA Signed
  #3799·huydhn opened Oct 5, 2026Contributor·

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• Cache Triton artifacts across process restarts

  CLA Signed
  #3774·Vtmpas opened Oct 5, 2026·

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• [pallas] Pipeline dynamic row-slab boundary tiles

  CLA Signed
  #3771·ethche opened Oct 5, 2026Contributor·

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• [pallas] Exclude HBM BlockSpecs from VMEM estimates

  CLA Signed
  #3770·ethche opened Oct 5, 2026Contributor·

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• Cute sequence skill completion 20260930

  CLA Signed
  #3737·yushangdi opened Oct 2, 2026Contributor·

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• [XPU] Bound timing events in interleaved_bench

  #3734·dev-tomek opened Oct 2, 2026·

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  1