feat(selector): fold small constants into i32.and immediates + encoder bound (VCR-RA-001)

[avrabe]

The first delta-emitting codegen transform on the allocator track (VCR-RA-001, epic #242). Consolidates the encoder-bound finding (was #249) with the folding that uses it.

The waste (measured, #248)

i32.const C; i32.and lowered to movw rN,#C; and rD,rA,rN even when C is small enough to be an AND immediate — the redundant materialization gale measured on flat_flight.

The fix

When the operand before i32.and is i32.const C with C ∈ 0..=0xFF and its movw is cleanly at the instruction tail (not spilled), fold to and rD, rA, #C and drop the materialization (foldable_bitwise_imm + drop_prev_const_materialization, mirroring the const-divisor pattern).

Encoder bound (was #249)

Bounded to 0..=0xFF because the encoder's AND-immediate path isn't yet ThumbExpandImm-complete (and r2,r0,#0x7e → 00 f0 7e 02 is correct; ≥0x100 would mis-encode). 0..=0xFF covers gale's int8 clamps. A pinning test documents the safe range; folding is guarded to it, so the encoder never sees an un-encodable immediate.

Measured delta

(p & 0x7e) + (p & 0x7e): 8 → 6 instructions — both movw #126 eliminated, each AND uses the immediate. Better than const-CSE (no materialization at all).

Full gate (codegen change)

• 282 lib tests + 20 integration suites pass.
• Three frozen differentials stay result-identical: control_step 0x00210A55, flight_seam 0x07FDF307, div_const 338/338.
• Tests: i32_and_folds_small_const_into_immediate (folded shape), i32_and_does_not_fold_out_of_range_const (0x140 stays a register operand — the encoder safety bound), and_immediate_encodes_correctly_in_byte_range... (encoder).
• CI fuzz (encoder_no_panic, wasm_ops_lower_or_error) adds totality.

Supersedes #248 (the evidence it pinned is now folded away) and subsumes #249 (the encoder-bound test is included here).

Part of #242.

🤖 Generated with Claude Code

[avrabe]

Built PR #250 and measured it on the G474RE — the first codegen-application delta, and it's correct on silicon:

bench	before	after #250	Δ	selfcheck
controller_step	169	168	−1 cyc	0x05e33e81 ✅
flat_flight	262	261	−1 cyc	0x07fdf307 ✅

Object-level: flat_flight 180→179 instrs (movw 33→32, .text 588→584 B); controller_step 120→119 (movw 27→26). So the fold fired and the result is bit-correct — the transform + my reflash loop are validated end-to-end. 🎉

One yield note: it folded exactly 1 AND-immediate per function, though both have ~3–4 & 0xFF byte-extractions in the packing. The movw cleanly at tail, not spilled guard is gating the rest (the other ANDs' movws are spilled or mid-sequence). So the bigger AND-fold yield is coupled to the spill work (VCR-RA-001) — once spill-under-pressure keeps those consts resident, more sites qualify. And per the 262→103 gap decomposition, the dominant levers are still ahead: const-CSE on the #0x7e/#0x7f clamp bounds (×6 each), mul+add→mla fusion, and tighter clamp lowering (18→6 IT-blocks).

Net: a clean, correct first step. Both microbenches stay frozen-and-staged; I'll post the delta for each subsequent transform as it lands.

[codecov]

Codecov Report

❌ Patch coverage is 95.09804% with 5 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
crates/synth-synthesis/src/instruction_selector.rs	94.50%	5 Missing ⚠️

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