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[Mips][MSA] Fix commutability of unordered comparisons #228567

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Merged
FlyGoat merged 1 commit into from
Oct 3, 2026
+41 −20
Merged

[Mips][MSA] Fix commutability of unordered comparisons #228567

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12 changes: 4 additions & 8 deletions llvm/lib/Target/Mips/MipsMSAInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1891,15 +1891,11 @@ class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
IsCommutable;

class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
IsCommutable;
class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
IsCommutable;
class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>;
class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>;

class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
IsCommutable;
class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
IsCommutable;
class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>;
class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>;

class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
IsCommutable;
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49 changes: 37 additions & 12 deletions llvm/test/CodeGen/Mips/msa/compare_float.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -357,67 +357,92 @@ define void @ugt_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
ret void
}

;; MachineCSE must not merge comparisons with reversed operands.
define void @ule_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: ule_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: ld.w $w0, 0($6)
; CHECK-NEXT: ld.w $w1, 0($5)
; CHECK-NEXT: fcule.w $w0, $w1, $w0
; CHECK-NEXT: ld.w $w0, 0($5)
; CHECK-NEXT: ld.w $w1, 0($6)
; CHECK-NEXT: fcule.w $w2, $w1, $w0
; CHECK-NEXT: st.w $w2, 16($4)
; CHECK-NEXT: fcule.w $w0, $w0, $w1
; CHECK-NEXT: jr $ra
; CHECK-NEXT: st.w $w0, 0($4)
%1 = load <4 x float>, ptr %a
%2 = load <4 x float>, ptr %b
%3 = fcmp ule <4 x float> %1, %2
%4 = sext <4 x i1> %3 to <4 x i32>
store <4 x i32> %4, ptr %c
%5 = fcmp ule <4 x float> %2, %1
%6 = sext <4 x i1> %5 to <4 x i32>
%7 = getelementptr <4 x i32>, ptr %c, i32 1
store <4 x i32> %6, ptr %7
ret void
}

define void @ule_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: ule_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: ld.d $w0, 0($6)
; CHECK-NEXT: ld.d $w1, 0($5)
; CHECK-NEXT: fcule.d $w0, $w1, $w0
; CHECK-NEXT: ld.d $w0, 0($5)
; CHECK-NEXT: ld.d $w1, 0($6)
; CHECK-NEXT: fcule.d $w2, $w1, $w0
; CHECK-NEXT: st.d $w2, 16($4)
; CHECK-NEXT: fcule.d $w0, $w0, $w1
; CHECK-NEXT: jr $ra
; CHECK-NEXT: st.d $w0, 0($4)
%1 = load <2 x double>, ptr %a
%2 = load <2 x double>, ptr %b
%3 = fcmp ule <2 x double> %1, %2
%4 = sext <2 x i1> %3 to <2 x i64>
store <2 x i64> %4, ptr %c
%5 = fcmp ule <2 x double> %2, %1
%6 = sext <2 x i1> %5 to <2 x i64>
%7 = getelementptr <2 x i64>, ptr %c, i32 1
store <2 x i64> %6, ptr %7
ret void
}

define void @ult_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: ult_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: ld.w $w0, 0($6)
; CHECK-NEXT: ld.w $w1, 0($5)
; CHECK-NEXT: fcult.w $w0, $w1, $w0
; CHECK-NEXT: ld.w $w0, 0($5)
; CHECK-NEXT: ld.w $w1, 0($6)
; CHECK-NEXT: fcult.w $w2, $w1, $w0
; CHECK-NEXT: st.w $w2, 16($4)
; CHECK-NEXT: fcult.w $w0, $w0, $w1
; CHECK-NEXT: jr $ra
; CHECK-NEXT: st.w $w0, 0($4)
%1 = load <4 x float>, ptr %a
%2 = load <4 x float>, ptr %b
%3 = fcmp ult <4 x float> %1, %2
%4 = sext <4 x i1> %3 to <4 x i32>
store <4 x i32> %4, ptr %c
%5 = fcmp ult <4 x float> %2, %1
%6 = sext <4 x i1> %5 to <4 x i32>
%7 = getelementptr <4 x i32>, ptr %c, i32 1
store <4 x i32> %6, ptr %7
ret void
}

define void @ult_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: ult_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: ld.d $w0, 0($6)
; CHECK-NEXT: ld.d $w1, 0($5)
; CHECK-NEXT: fcult.d $w0, $w1, $w0
; CHECK-NEXT: ld.d $w0, 0($5)
; CHECK-NEXT: ld.d $w1, 0($6)
; CHECK-NEXT: fcult.d $w2, $w1, $w0
; CHECK-NEXT: st.d $w2, 16($4)
; CHECK-NEXT: fcult.d $w0, $w0, $w1
; CHECK-NEXT: jr $ra
; CHECK-NEXT: st.d $w0, 0($4)
%1 = load <2 x double>, ptr %a
%2 = load <2 x double>, ptr %b
%3 = fcmp ult <2 x double> %1, %2
%4 = sext <2 x i1> %3 to <2 x i64>
store <2 x i64> %4, ptr %c
%5 = fcmp ult <2 x double> %2, %1
%6 = sext <2 x i1> %5 to <2 x i64>
%7 = getelementptr <2 x i64>, ptr %c, i32 1
store <2 x i64> %6, ptr %7
ret void
}

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