[FlyGoat]

Remove IsCommutable from FCULT_W/D and FCULE_W/D, whose predicates are directional. Extend the existing floating-point comparison tests to check that reversed comparisons produce separate results.

Fixes: #228422

[llvmorg-github-actions]

@llvm/pr-subscribers-backend-mips

Author: Jiaxun Yang (FlyGoat)

Changes

Remove IsCommutable from FCULT_W/D and FCULE_W/D, whose predicates are directional. Extend the existing floating-point comparison tests to check that reversed comparisons produce separate results.

Fixes: #228422

---

Full diff: https://github.com/llvm/llvm-project/pull/228567.diff

2 Files Affected:

• (modified) llvm/lib/Target/Mips/MipsMSAInstrInfo.td (+4-8)
• (modified) llvm/test/CodeGen/Mips/msa/compare_float.ll (+37-12)

diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index 3ecb079fbcded..220c999ca6e3b 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -1891,15 +1891,11 @@ class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
                      IsCommutable;
 
-class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
-                     IsCommutable;
-class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
-                     IsCommutable;
+class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>;
+class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>;
 
-class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
-                     IsCommutable;
-class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
-                     IsCommutable;
+class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>;
+class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>;
 
 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
                     IsCommutable;
diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll
index d06131bd09627..5c2f72160195a 100644
--- a/llvm/test/CodeGen/Mips/msa/compare_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll
@@ -357,12 +357,15 @@ define void @ugt_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
   ret void
 }
 
+;; MachineCSE must not merge comparisons with reversed operands.
 define void @ule_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
 ; CHECK-LABEL: ule_v4f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld.w $w0, 0($6)
-; CHECK-NEXT:    ld.w $w1, 0($5)
-; CHECK-NEXT:    fcule.w $w0, $w1, $w0
+; CHECK-NEXT:    ld.w $w0, 0($5)
+; CHECK-NEXT:    ld.w $w1, 0($6)
+; CHECK-NEXT:    fcule.w $w2, $w1, $w0
+; CHECK-NEXT:    st.w $w2, 16($4)
+; CHECK-NEXT:    fcule.w $w0, $w0, $w1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    st.w $w0, 0($4)
   %1 = load <4 x float>, ptr %a
@@ -370,15 +373,21 @@ define void @ule_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
   %3 = fcmp ule <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
   store <4 x i32> %4, ptr %c
+  %5 = fcmp ule <4 x float> %2, %1
+  %6 = sext <4 x i1> %5 to <4 x i32>
+  %7 = getelementptr <4 x i32>, ptr %c, i32 1
+  store <4 x i32> %6, ptr %7
   ret void
 }
 
 define void @ule_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
 ; CHECK-LABEL: ule_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld.d $w0, 0($6)
-; CHECK-NEXT:    ld.d $w1, 0($5)
-; CHECK-NEXT:    fcule.d $w0, $w1, $w0
+; CHECK-NEXT:    ld.d $w0, 0($5)
+; CHECK-NEXT:    ld.d $w1, 0($6)
+; CHECK-NEXT:    fcule.d $w2, $w1, $w0
+; CHECK-NEXT:    st.d $w2, 16($4)
+; CHECK-NEXT:    fcule.d $w0, $w0, $w1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    st.d $w0, 0($4)
   %1 = load <2 x double>, ptr %a
@@ -386,15 +395,21 @@ define void @ule_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
   %3 = fcmp ule <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
   store <2 x i64> %4, ptr %c
+  %5 = fcmp ule <2 x double> %2, %1
+  %6 = sext <2 x i1> %5 to <2 x i64>
+  %7 = getelementptr <2 x i64>, ptr %c, i32 1
+  store <2 x i64> %6, ptr %7
   ret void
 }
 
 define void @ult_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
 ; CHECK-LABEL: ult_v4f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld.w $w0, 0($6)
-; CHECK-NEXT:    ld.w $w1, 0($5)
-; CHECK-NEXT:    fcult.w $w0, $w1, $w0
+; CHECK-NEXT:    ld.w $w0, 0($5)
+; CHECK-NEXT:    ld.w $w1, 0($6)
+; CHECK-NEXT:    fcult.w $w2, $w1, $w0
+; CHECK-NEXT:    st.w $w2, 16($4)
+; CHECK-NEXT:    fcult.w $w0, $w0, $w1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    st.w $w0, 0($4)
   %1 = load <4 x float>, ptr %a
@@ -402,15 +417,21 @@ define void @ult_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
   %3 = fcmp ult <4 x float> %1, %2
   %4 = sext <4 x i1> %3 to <4 x i32>
   store <4 x i32> %4, ptr %c
+  %5 = fcmp ult <4 x float> %2, %1
+  %6 = sext <4 x i1> %5 to <4 x i32>
+  %7 = getelementptr <4 x i32>, ptr %c, i32 1
+  store <4 x i32> %6, ptr %7
   ret void
 }
 
 define void @ult_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
 ; CHECK-LABEL: ult_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld.d $w0, 0($6)
-; CHECK-NEXT:    ld.d $w1, 0($5)
-; CHECK-NEXT:    fcult.d $w0, $w1, $w0
+; CHECK-NEXT:    ld.d $w0, 0($5)
+; CHECK-NEXT:    ld.d $w1, 0($6)
+; CHECK-NEXT:    fcult.d $w2, $w1, $w0
+; CHECK-NEXT:    st.d $w2, 16($4)
+; CHECK-NEXT:    fcult.d $w0, $w0, $w1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    st.d $w0, 0($4)
   %1 = load <2 x double>, ptr %a
@@ -418,6 +439,10 @@ define void @ult_v2f64(ptr %c, ptr %a, ptr %b) nounwind {
   %3 = fcmp ult <2 x double> %1, %2
   %4 = sext <2 x i1> %3 to <2 x i64>
   store <2 x i64> %4, ptr %c
+  %5 = fcmp ult <2 x double> %2, %1
+  %6 = sext <2 x i1> %5 to <2 x i64>
+  %7 = getelementptr <2 x i64>, ptr %c, i32 1
+  store <2 x i64> %6, ptr %7
   ret void
 }