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[mono] Reenable some amd64 intrinsic tests, enable amd64 ISA extensions when AOTing, several intrinsics fixes #53752

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Merged
imhameed merged 16 commits into from
Jun 13, 2021
Merged

[mono] Reenable some amd64 intrinsic tests, enable amd64 ISA extensions when AOTing, several intrinsics fixes #53752

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855a27e
[mono] Reenable some amd64 intrinsic tests and enable a bunch of ISA …
imhameed Jun 5, 2021
4b84925
Consolidate SSE shuffle constant unrolling
imhameed Jun 5, 2021
e036401
Fix intrinsification for MathF.Round.
imhameed Jun 10, 2021
32eecfa
Run the JIT parts (!) of the AOT tests with LLVM
imhameed Jun 11, 2021
b073bd7
Clean up intrinsic group lookup
imhameed Jun 11, 2021
4d7b219
The "not" SSE comparions are unordered
imhameed Jun 11, 2021
b682d35
Fix LoadAndDuplicateToVector128
imhameed Jun 11, 2021
9a06323
Remove OP_DPPS; it is unused
imhameed Jun 12, 2021
de83cf3
Implement constant unrolling for Sse41.DotProduct
imhameed Jun 12, 2021
c83be20
Zero is part of the domain of lzcnt and shouldn't yield an undef
imhameed Jun 12, 2021
bfafb8d
Implement constant unrolling for Sse41.Blend
imhameed Jun 12, 2021
9f2c3bf
Unify amd64/arm64 vector extraction handling
imhameed Jun 12, 2021
d94aec3
Disable JIT/Regression/CLR-x86-JIT/V1.1-M1-Beta1/b143840 when running…
imhameed Jun 12, 2021
ddc11c5
Disable finalizearray when running with mono LLVM AOT
imhameed Jun 13, 2021
06a7164
Disable Vector256_1/Vector128_1 tests on wasm
imhameed Jun 13, 2021
f525f80
???
imhameed Jun 11, 2021
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1 change: 1 addition & 0 deletions eng/pipelines/common/templates/runtimes/run-test-job.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -324,6 +324,7 @@ jobs:
osSubgroup: ${{ parameters.osSubgroup}}
runtimeFlavorDisplayName: ${{ parameters.runtimeFlavorDisplayName }}
shouldContinueOnError: ${{ parameters.shouldContinueOnError }}
runtimeVariant: ${{ parameters.runtimeVariant }}

${{ if eq(variables['System.TeamProject'], 'public') }}:
creator: $(Build.DefinitionName)
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2 changes: 0 additions & 2 deletions src/mono/mono/mini/cpu-amd64.md
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Expand Up @@ -779,9 +779,7 @@ extract_i4: dest:i src1:x len:5
extract_i8: dest:i src1:x len:9

extract_i2: dest:i src1:x len:13
extract_u2: dest:i src1:x len:13
extract_i1: dest:i src1:x len:13
extract_u1: dest:i src1:x len:13
extract_r8: dest:f src1:x len:5

iconv_to_r4_raw: dest:f src1:i len:10
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2 changes: 0 additions & 2 deletions src/mono/mono/mini/cpu-x86.md
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Expand Up @@ -631,9 +631,7 @@ iconv_to_x: dest:x src1:i len:4
extract_i4: dest:i src1:x len:4

extract_i2: dest:i src1:x len:10
extract_u2: dest:i src1:x len:10
extract_i1: dest:i src1:x len:10
extract_u1: dest:i src1:x len:10
extract_r8: dest:f src1:x len:8

insert_i2: dest:x src1:x src2:i len:5 clob:1
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9 changes: 6 additions & 3 deletions src/mono/mono/mini/intrinsics.c
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Expand Up @@ -140,15 +140,18 @@ llvm_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSign
}
#if defined(TARGET_X86) || defined(TARGET_AMD64)
else if (!strcmp (cmethod->name, "Round") && (mini_get_cpu_features (cfg) & MONO_CPU_X86_SSE41) != 0) {
// special case: emit vroundps for MathF.Round directly instead of what llvm.round.f32 emits
// special case: emit vroundss for MathF.Round directly instead of what llvm.round.f32 emits
// to align with CoreCLR behavior
int xreg = alloc_xreg (cfg);
EMIT_NEW_UNALU (cfg, ins, OP_FCONV_TO_R4_X, xreg, args [0]->dreg);
EMIT_NEW_UNALU (cfg, ins, OP_SSE41_ROUNDS, xreg, xreg);
int xround = alloc_xreg (cfg);
EMIT_NEW_BIALU (cfg, ins, OP_SSE41_ROUNDS, xround, xreg, xreg);
ins->inst_c0 = 0x4; // vroundss xmm0, xmm0, xmm0, 0x4 (mode for rounding)
ins->inst_c1 = MONO_TYPE_R4;
int dreg = alloc_freg (cfg);
EMIT_NEW_UNALU (cfg, ins, OP_EXTRACT_R4, dreg, xreg);
EMIT_NEW_UNALU (cfg, ins, OP_EXTRACT_R4, dreg, xround);
ins->inst_c0 = 0;
ins->inst_c1 = MONO_TYPE_R4;
return ins;
}
#endif
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12 changes: 6 additions & 6 deletions src/mono/mono/mini/mini-amd64.c
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Expand Up @@ -4076,8 +4076,8 @@ mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)

case OP_XEXTRACT_R4:
case OP_XEXTRACT_R8:
case OP_XEXTRACT_I32:
case OP_XEXTRACT_I64: {
case OP_XEXTRACT_I4:
case OP_XEXTRACT_I8: {
// TODO
g_assert_not_reached();
break;
Expand Down Expand Up @@ -7235,19 +7235,17 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
}
break;
case OP_EXTRACT_I1:
case OP_EXTRACT_U1:
amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
if (ins->inst_c0)
amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
amd64_widen_reg (code, ins->dreg, ins->dreg, ins->inst_c1 == MONO_TYPE_I1, FALSE);
break;
case OP_EXTRACT_I2:
case OP_EXTRACT_U2:
/*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
if (ins->inst_c0)
amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->inst_c1 == MONO_TYPE_I2, TRUE, 4);
break;
case OP_EXTRACT_R8:
if (ins->inst_c0)
Expand Down Expand Up @@ -8965,6 +8963,8 @@ mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMetho
ins->inst_c1 = MONO_TYPE_R8;
int dreg = alloc_freg (cfg);
EMIT_NEW_UNALU (cfg, ins, OP_EXTRACT_R8, dreg, xreg);
ins->inst_c0 = 0;
ins->inst_c1 = MONO_TYPE_R8;
return ins;
}
}
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