pes_vending_machine

• Creating a Verilog simulation of a parking ticket vending machine that accepts Rs 5 and Rs 10 coins and dispenses a Rs 20 ticket involves designing a digital system that manages coin inputs, validates the coin values, calculates the total amount, and dispenses the ticket when the required amount is reached.
• The machine is implemented using principles of a Finite State Machine, which hops across different states while keeping track of the input coins.

Tools Used in RTL to GLS flow are:

1. iVerilog:

• A free and open-source Verilog simulation and synthesis tool.
• Part of the Icarus Verilog project.
• Utilized for simulating Verilog hardware description language code.
• It enables testing the design using a test bench, which applies stimulus to verify the functionality.
• Monitors input changes and evaluates corresponding output responses.

2. GTKwave:

• A free and open-source waveform viewer.
• Mainly used for visualizing simulation results produced by digital simulation tools such as Icarus Verilog.

3. Yosys:

• An open-source framework designed for Verilog RTL synthesis.
• Widely employed in digital design for converting high-level digital circuit descriptions into gate-level representations.
• Helps transform behavioral descriptions (e.g., Verilog code) into netlists, offering detailed information about the digital logic through gates and their connections.

Step 1

• To initiate the flow, the initial step involves creating a Verilog code that encapsulates the idea. This code is saved as a ".v" file. Simultaneously, a testbench is crafted for this file. Both the Verilog code and its corresponding testbench are then loaded into the iVerilog tool. By doing so, the tool can execute the simulation and generate a dump file, allowing us to visualize the waveform. vim pes_ptvm.v

vim pes_ptvm_tb.v

Step 2

iverilog pes_ptvm.v pes_ptvm_tb.v  
ls

./a.out
gtkwave dump.vcd

Pre-Synthesis result

RTL Synthesis

• In RTL synthesis:
  • The RTL design is transformed into a gate-level netlist with designer-specified constraints.
  • The design is converted from abstract RTL to logic gates.
  • The logic gates are mapped to technology-dependent gates from libraries.
  • The mapped netlist is optimized while adhering to designer constraints. = To perform RTL synthesis:
  • Utilize the Yosys tool to generate a netlist.
  • Run the generated netlist using iverilog, along with the ".net" file and the testbench, to create an executable file "a.out."

read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog pes_ptvm.v
synth -top pes_ptvm

abc -liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
show

To get ".net file"

• In the yosys tool

write_verilog pes_ptvm_net.v
!vim pes_ptvm_net.v

Gate Level Simulation

iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v pes_ptvm_net.v pes_vtvm_tb.v
ls
gtkwave dump.vcd

Physical Design

Physical design is the essential procedure that converts an abstract depiction of an electronic system, like an integrated circuit or computer chip, into a practical layout fit for manufacturing. This intricate process involves a series of stages for organizing and structuring different components, such as transistors, wiring, and connections, on a semiconductor material.

Key facets of physical design encompass:

1. Floorplanning: Defining the spatial arrangement of components and modules within the chip's layout.
2. Placement: Positioning individual elements like transistors and logic gates efficiently on the semiconductor substrate.
3. Routing: Establishing the interconnections or wiring between these components to facilitate data flow.
4. Clock Tree Synthesis (CTS): Structuring the clock distribution network to ensure precise synchronization throughout the chip.
5. Power Planning: Managing power distribution and consumption to maintain optimal operation and minimize energy usage.
6. Signal Integrity Analysis: Assessing the integrity of signals during transmission to prevent interference or distortion.
7. Timing Analysis: Evaluating the timing of signal propagation to meet performance requirements and minimize delays.
8. Design for Testability (DFT): Incorporating features that simplify testing and fault detection during chip production.
9. Physical Verification: Conducting rigorous checks to confirm that the physical design adheres to design rules and is free from errors.
10. Package Design: Creating the external packaging of the chip, considering factors like heat dissipation and connectivity.

Installation

ngspice

• Download the tarball from https://sourceforge.net/projects/ngspice/files/ to a local directory

cd $HOME
sudo apt-get install libxaw7-dev
tar -zxvf ngspice-41.tar.gz
cd ngspice-41
mkdir release
cd release
../configure  --with-x --with-readline=yes --disable-debug
sudo make
sudo make install

magic

sudo apt-get install m4
sudo apt-get install tcsh
sudo apt-get install csh
sudo apt-get install libx11-dev
sudo apt-get install tcl-dev tk-dev
sudo apt-get install libcairo2-dev
sudo apt-get install mesa-common-dev libglu1-mesa-dev
sudo apt-get install libncurses-dev
git clone https://github.com/RTimothyEdwards/magic
cd magic
./configure
sudo make
sudo make install

OpenLane

sudo apt-get update
sudo apt-get upgrade
sudo apt install -y build-essential python3 python3-venv python3-pip make git

sudo apt install apt-transport-https ca-certificates curl software-properties-common
curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /usr/share/keyrings/docker-archive-keyring.gpg

echo "deb [arch=amd64 signed-by=/usr/share/keyrings/docker-archive-keyring.gpg] https://download.docker.com/linux/ubuntu $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null

sudo apt update
sudo apt install docker-ce docker-ce-cli containerd.io
sudo docker run hello-world
sudo groupadd docker
sudo usermod -aG docker $USER
sudo reboot 
# After reboot
docker run hello-world (should show you the output under 'Example Output' in https://hub.docker.com/_/hello-world)

- To install the PDKs and Tools
cd $HOME
git clone https://github.com/The-OpenROAD-Project/OpenLane
cd OpenLane
make
make test

Step 1

• To begin the physical design process, we must create the design file for the "pes_vending_machine" project. This entails having the "pes_vending_machine.v" file and access to the Skywater Process Design Kit (PDK), which contains all the necessary foundry-provided PDK-related files. To accomplish this, we follow these steps within the Openlane design directory:
  1. Create a folder called "pes_vending_machine" within the design directory.
  2. Within the "pes_vending_machine" folder, establish two subfolders named "src" and "config.tcl."

To make the config.tcl file we type the following: vim config.tcl

set ::env(DESIGN_NAME) "pes_vending_machine"

set ::env(VERILOG_FILES) "./designs/pes_vending_machine/src/pes_vending_machine.v"

set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)

set filename $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
        source $filename
}

• after this, we go to the src file and add the pes_vending_machine.v file that we generated from Yosys in RTL synthesis and the required PDKs for our design.

Step 2

• To initiate Openlane, we invoke it by executing the following commands

cd Desktop/work/tools/openlane_working_dir/openlane
docker
./flow.tcl -interactive
package require openlane

• Once we invoke OpenLane it should look the same as shown below:

• After launching OpenLane, the next step is to prepare the specific design we want to work on. In this case, given that we're dealing with a vending machine finite state machine (FSM), we can use the following command to prepare the design prep -design pes_vending_machine

Step 3

• after preparing the design we now do the first process of physical design which is run_synthesis
• When we execute the "run_synthesis" command in OpenLane, it generates statistics related to the synthesis process, specifically for the "ring_counter." This synthesis operation is marked as successful. During this operation, OpenLane creates a "runs" directory, which contains various logs, results, and reports for the design file that underwent synthesis.
• The run_synthesis statistics are as below

• The runs keep track of the process we do in the openlane as shown below:

Step 4

• Following the synthesis stage, the next step is to create a floorplan for the ring counter. This is achieved by using the "run_floorplan" command. When you run this command, it generates a "floorplan.def" file, which can be utilized to visualize the design using the Magic tool.
• Upon successful completion of the floorplan operation, you will find a file named "pes_vending_machine.floorplan.def" within the results directory, as demonstrated below:

• This indicates that the "run_floorplan" operation was successful, and now you can utilize the generated floorplan file to view the layout using the Magic tool.
• To view the floorplan layout with the Magic tool, you can use the following command: magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def ring_counter.floorplan.def &
• In this command:
  • -T specifies the tech file.
  • & is used to run the command in the background, preventing prompts from appearing in the terminal.

• To inspect the contents of the generated floorplan file, "pes_vending_machine.floorplan.def," and check for any issues, particularly related to the utilization parameter, we use the following command: cat pes_vending_machine.floorplan.def
• This command allows you to view the contents of the floorplan file, and the output will be displayed in the terminal. You can then analyze the file to identify and address any potential issues with the floorplan definition.

Floorplan & Placement

• We invoke OoenLane

cd OpenLane
make mount
./flow.tcl -design pes_vending_machine

• To locate the pes_vending_machine.def file for floorplan we type the following command

cd OpenLane/designs/pes_vending_machine/runs/RUN_2023.11.03_05.18.10/results/floorplan
ls

• now to view the floorplan we use the following command

magic -T /home/bavitha/.volare/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read pes_sdw.def &

• For placement first change the directory to

cd OpenLane/designs/pes_vending_machine/runs/RUN_2023.11.03_05.32.49/results/placement
magic -T /home/anirudh/.volare/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read pes_vending_machine.def &

Clock tree synthesis

run_cts

Routing

magic -T /home/anirudh/.volare/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read pes_vending_machine.def &

Statistics

• Synthesis

• Floorplan

• Placement

• Clock Tree Synthesis

• Routing