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1. Vending_Machine_FSM Vending_Machine_FSM Public

   The design and optimization of a vending machine FSM were accomplished using iVerilog, GTKwave, and Yosys

   Verilog 1

2. Layered-Testbench Layered-Testbench Public

   This project implements a layered SystemVerilog testbench to verify a synchronous 4-bit adder. The verification environment is modular and self-checking, demonstrating core verification principles …

   SystemVerilog 2

3. Single-Cycle-RISC-V-Processor Single-Cycle-RISC-V-Processor Public

   This repository contains a single-cycle RISC-V processor designed in SystemVerilog for a 5th-semester project. It supports a subset of the RISC-V ISA and executes one instruction per clock cycle. T…

   SystemVerilog

4. Semiconductor_Packaging_Ansys Semiconductor_Packaging_Ansys Public

   This repository offers a comprehensive end-to-end overview of semiconductor packaging, spanning foundational concepts to advanced 3D integration and ANSYS-based design modeling. It integrates theor…

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