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[ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang and relaxed has_tilelang - #51159
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Signed-off-by: Felix Marty <Felix.Marty@amd.com>
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/ci run |
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✅ Triggered Buildkite CI #82487 for commit |
| def _tilelang_jit(kernel_function: Callable[..., Any]) -> Callable[..., Any]: | ||
| """Apply `tilelang.jit`, deferring until first call on ROCm. | ||
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| ROCm defers JIT decoration so importing this module does not require | ||
| TileLang immediately. CUDA keeps the eager decoration behavior. | ||
| """ | ||
| if not current_platform.is_rocm(): | ||
| _ensure_tilelang_imported() | ||
| return tilelang.jit(pass_configs=_get_pass_configs())(kernel_function) | ||
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| compiled_kernel: Callable[..., Any] | None = None | ||
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| @functools.wraps(kernel_function) | ||
| def wrapper(*args: Any, **kwargs: Any) -> Any: | ||
| nonlocal compiled_kernel | ||
| if compiled_kernel is None: | ||
| _ensure_tilelang_imported() | ||
| compiled_kernel = tilelang.jit(pass_configs=_get_pass_configs())( | ||
| kernel_function | ||
| ) | ||
| return compiled_kernel(*args, **kwargs) | ||
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| return wrapper |
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How about making a tilelang_utils similar to triton_utils?
vllm/vllm/triton_utils/__init__.py
Lines 1 to 26 in a9b39d6
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Fixed in fa9cc9e, thank you!
Also made from vllm.tilelang_utils import tilelang import pattern compulsory, similar to triton.
Co-authored-by: Claude Signed-off-by: Felix Marty <Felix.Marty@amd.com>
tilelang importtilelang import through its import from vllm.tilelang_utils import tilelang
Co-authored-by: Claude Signed-off-by: Felix Marty <Felix.Marty@amd.com>
tilelang import through its import from vllm.tilelang_utils import tilelangtilelang import through its import from vllm.tilelang_utils import tilelang and relaxed has_tilelang
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/ci run |
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✅ Triggered Buildkite CI #82879 for commit |
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/ci retry |
Isotr0py
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Anyway, let's land this to fix the broken model first.
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
…om libhip_stub.so Signed-off-by: Felix Marty <Felix.Marty@amd.com>
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Documentation preview: https://vllm--51159.org.readthedocs.build/en/51159/ |
@tjtanaa @Fangzhou-Ai actually, I do not quite get where This is guarded on: vllm/vllm/models/deepseek_v4/amd/model.py Lines 398 to 400 in 34735ac where vllm/vllm/model_executor/layers/mhc.py Line 29 in 34735ac Moreover:
@tjtanaa this looks safe to me after ensuring the vLLM CI / AMD CI runs on it. But from what I found there is no registered DS-v4 test that exercises a tilelang path. |
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@fxmarty-amd In realistic we never use the tilelang mHC, AITER mHC is always preferred. |
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/ci run |
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✅ @fxmarty-amd, CI is now available for this PR.
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✅ Triggered Buildkite CI #83743 for commit |
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
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/ci run |
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✅ Triggered Buildkite CI #83748 for commit |
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buildkite/amd-ci looks sane to me (although it has some skipped test groups) |
…_utils import tilelang` and relaxed `has_tilelang` (vllm-project#51159) Signed-off-by: Felix Marty <Felix.Marty@amd.com> Co-authored-by: Andreas Karatzas <akaratza@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
…_utils import tilelang` and relaxed `has_tilelang` (vllm-project#51159) Signed-off-by: Felix Marty <Felix.Marty@amd.com> Co-authored-by: Andreas Karatzas <akaratza@amd.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Purpose
Fixes #51151
This PR introduces
vllm.tilelang_utilsand prevents directtilelangimports.Avoid importing TileLang during ROCm module import, because importing TileLang can load wrongful/bugged TVM and HIP stub symbols into the global process scope before AITER loads its JIT modules.
This changes
_tilelang_jitso ROCm appliestilelang.jitlazily on first kernel call, while non-ROCm keeps eager JIT decoration.This PR is AI-assisted.
Proper fixes in followups need to be:
tilelangor TVM to fix the wrongful symbol load._has_moduledoes not import modules [Feature]:vllm.utils.import_util._has_moduleshould not import modules #51162Test Plan
python tools/pre_commit/check_forbidden_imports.py --test-regexpytest tests/kernels/test_mhc_tilelang_jit.py -vAdded new test to verify that CUDA applies
tilelang.jiteagerly, ROCm deferstilelang.jituntil first call, and the ROCm wrapper caches the compiled kernel.that is failing on
mainfollowing #50879, and which surfaces the issue #51151Test Result
test_mhc_tilelang_jit.pypass on MI350.tests/quantization/test_online.pyas well on MI300 (previous failing case)python tools/pre_commit/check_forbidden_imports.py --test-regexpasses as well.