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[ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang and relaxed has_tilelang - #51159

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AndreasKaratzas merged 14 commits into
vllm-project:mainfrom
fxmarty-amd:tilelang-lazy-import
Aug 13, 2026
Merged

AndreasKaratzas merged 14 commits into
vllm-project:mainfrom
fxmarty-amd:tilelang-lazy-import

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@fxmarty-amd

@fxmarty-amd fxmarty-amd commented Aug 5, 2026 •

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Purpose

Fixes #51151

This PR introduces vllm.tilelang_utils and prevents direct tilelang imports.

Avoid importing TileLang during ROCm module import, because importing TileLang can load wrongful/bugged TVM and HIP stub symbols into the global process scope before AITER loads its JIT modules.

This changes _tilelang_jit so ROCm applies tilelang.jit lazily on first kernel call, while non-ROCm keeps eager JIT decoration.

This PR is AI-assisted.

Proper fixes in followups need to be:

Test Plan

  • python tools/pre_commit/check_forbidden_imports.py --test-regex
  • pytest tests/kernels/test_mhc_tilelang_jit.py -v

Added new test to verify that CUDA applies tilelang.jit eagerly, ROCm defers tilelang.jit until first call, and the ROCm wrapper caches the compiled kernel.

VLLM_ROCM_USE_AITER=1 HIP_VISIBLE_DEVICES=1 pytest tests/quantization/test_online.py::test_online_quantization[True-fp8_per_tensor-None-Fp8PerTensorOnlineLinearMethod-Fp8PerTensorOnlineMoEMethod] -s -vvvvv

that is failing on main following #50879, and which surfaces the issue #51151

Test Result

test_mhc_tilelang_jit.py pass on MI350.

tests/quantization/test_online.py as well on MI300 (previous failing case)

python tools/pre_commit/check_forbidden_imports.py --test-regex passes as well.

Signed-off-by: Felix Marty <Felix.Marty@amd.com>

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Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

@mergify mergify Bot added the rocm Related to AMD ROCm label Aug 5, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD Aug 5, 2026
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
@AndreasKaratzas

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/ci run

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github-actions Bot commented Aug 5, 2026

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✅ Triggered Buildkite CI #82487 for commit 467d3390f9b2.

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
Comment on lines +71 to +93
def _tilelang_jit(kernel_function: Callable[..., Any]) -> Callable[..., Any]:
"""Apply `tilelang.jit`, deferring until first call on ROCm.

ROCm defers JIT decoration so importing this module does not require
TileLang immediately. CUDA keeps the eager decoration behavior.
"""
if not current_platform.is_rocm():
_ensure_tilelang_imported()
return tilelang.jit(pass_configs=_get_pass_configs())(kernel_function)

compiled_kernel: Callable[..., Any] | None = None

@functools.wraps(kernel_function)
def wrapper(*args: Any, **kwargs: Any) -> Any:
nonlocal compiled_kernel
if compiled_kernel is None:
_ensure_tilelang_imported()
compiled_kernel = tilelang.jit(pass_configs=_get_pass_configs())(
kernel_function
)
return compiled_kernel(*args, **kwargs)

return wrapper

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How about making a tilelang_utils similar to triton_utils?

# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
from typing import TYPE_CHECKING
from vllm.triton_utils.importing import (
HAS_TRITON,
TritonLanguagePlaceholder,
TritonPlaceholder,
)
if TYPE_CHECKING or HAS_TRITON:
import triton
import triton.language as tl
import triton.language.extra.libdevice as tldevice
from triton.experimental import gluon
from triton.experimental.gluon import language as gl
from triton.language.core import _aggregate as aggregate # noqa: E501
else:
triton = TritonPlaceholder()
tl = TritonLanguagePlaceholder()
tldevice = TritonLanguagePlaceholder()
gluon = TritonLanguagePlaceholder()
gl = TritonLanguagePlaceholder()
aggregate = TritonLanguagePlaceholder()
from vllm.triton_utils.tensor_descriptor import use_tensor_descriptor

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Fixed in fa9cc9e, thank you!

Also made from vllm.tilelang_utils import tilelang import pattern compulsory, similar to triton.

Co-authored-by: Claude
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
@fxmarty-amd
fxmarty-amd requested a review from hmellor as a code owner August 6, 2026 10:11
@fxmarty-amd fxmarty-amd changed the title [ROCm] Defer tilelang import [ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang Aug 6, 2026
Co-authored-by: Claude
Signed-off-by: Felix Marty <Felix.Marty@amd.com>
@fxmarty-amd fxmarty-amd changed the title [ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang [ROCm] Defer tilelang import through its import from vllm.tilelang_utils import tilelang and relaxed has_tilelang Aug 6, 2026
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/ci run

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github-actions Bot commented Aug 7, 2026

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✅ Triggered Buildkite CI #82879 for commit e0903f35e0b2.

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/ci retry

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Anyway, let's land this to fix the broken model first.

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
…om libhip_stub.so

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
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mergify Bot commented Aug 12, 2026

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Documentation preview: https://vllm--51159.org.readthedocs.build/en/51159/

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@fxmarty-amd @rasmith can you try launching deepseek v4 as it is the only model that is relying on tilelang. Check the server logs for any traces of tilelang jit build to find out if we still have active path that is using tilelang.

@tjtanaa @Fangzhou-Ai actually, I do not quite get where self.use_fused_mhc -> _forward_fused_post_pre -> hc_pre/mhc_fused_post_pre -> torch.ops.vllm.mhc_fused_post_pre_tilelang is really used in #43950 - it looks to me the tilelang path is never exercised on tested MI300/MI325/MI350 code paths ?

This is guarded on:

self.use_fused_mhc = HAS_TILELANG_MHC and not (
HAS_AITER_MHC and self.hidden_size % 256 == 0
)

where

HAS_AITER_MHC = is_aiter_found_and_supported()
which simply checks if we are on CDNA > 2 (>=MI300).

Moreover:

  • deepseek-ai/DeepSeek-V4-Flash has hidden_size = 4096 => falls into aiter
  • deepseek-ai/DeepSeek-V4-Pro has hidden_size = 7168 => falls into aiter

@tjtanaa this looks safe to me after ensuring the vLLM CI / AMD CI runs on it. But from what I found there is no registered DS-v4 test that exercises a tilelang path.

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@fxmarty-amd In realistic we never use the tilelang mHC, AITER mHC is always preferred.

@tjtanaa tjtanaa added the ready ONLY add when PR is ready to merge/full CI is needed label Aug 13, 2026
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tjtanaa commented Aug 13, 2026

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/ci run

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✅ @fxmarty-amd, CI is now available for this PR.

  • /ci run starts a CI build.
  • /ci retry retries failed jobs in the CI build for the current PR head. If the current head has no CI build, it starts a new CI build for the current head containing only jobs that failed in the latest earlier CI build for this PR.
  • /ci cancel cancels scheduled or running CI builds for this PR branch.

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✅ Triggered Buildkite CI #83743 for commit 97f38dffc690.

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
@fxmarty-amd

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/ci run

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✅ Triggered Buildkite CI #83748 for commit a9a188702c7c.

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buildkite/amd-ci looks sane to me (although it has some skipped test groups)

@AndreasKaratzas
AndreasKaratzas merged commit c5b7c06 into vllm-project:main Aug 13, 2026
90 checks passed
@github-project-automation github-project-automation Bot moved this from Todo to Done in AMD Aug 13, 2026
zufangzhu pushed a commit to zufangzhu/vllm that referenced this pull request Aug 24, 2026
…_utils import tilelang` and relaxed `has_tilelang` (vllm-project#51159)

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Signed-off-by: Zhu, Zufang <zufang.zhu@intel.com>
michael-gpu pushed a commit to practical-inference/vllm-ampere-extended that referenced this pull request Oct 20, 2026
…_utils import tilelang` and relaxed `has_tilelang` (vllm-project#51159)

Signed-off-by: Felix Marty <Felix.Marty@amd.com>
Co-authored-by: Andreas Karatzas <akaratza@amd.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Labels

documentation Improvements or additions to documentation ready ONLY add when PR is ready to merge/full CI is needed rocm Related to AMD ROCm

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[Bug][Regression] #50879 causes wrongful hipMalloc to be loaded on ROCm due to tilelang load, causing tests and allocation failures

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