topology: sof-glk-cs42l42: add topology for cs42l42#4121
topology: sof-glk-cs42l42: add topology for cs42l42#4121lgirdwood merged 1 commit intothesofproject:mainfrom
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The machine driver is here: thesofproject/linux#2884 |
tools/topology/CMakeLists.txt
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looking at the commit message, could we use just one fine with two macros for the dailink and bitclock delay? Topologies are hard to maintain, and if we can factor it's best.
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sure, will avoid adding new topology file.
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Implement cs42l42 support in sof-glk-da7219.m4 file. Three conf files, sof-glk-da7219.conf, sof-glk-cs42l42.conf, and sof-glk-eq-da7219.conf are checked to make sure the topology files are generated correctly. |
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We can simplify further by modifying the machine driver and using SSPs first, then DMIC and last HDMI.
tools/topology/sof-glk-da7219.m4
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this is too complicated, there is no reason to reorder the BE dailinks, we can change the machine driver and first add the two SSP links, then DMIC and last HDMI. that way only the SSP number and configuration will change, and dmic/HDMI can be moved out of the conditional part.
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got it. will update the commits.
Add support for cs42l42 running on GLK boards. We add a 10 ms BCLK delay to the SSP_CONFIG_DATA of SSP2 since the codec PLL is locking on BCLK. Without the delay, there could be noise on TX path. Signed-off-by: Brent Lu <brent.lu@intel.com>
| SSP_CLOCK(bclk, 3072000, codec_slave), | ||
| SSP_CLOCK(fsync, 48000, codec_slave), | ||
| SSP_TDM(2, 32, 3, 3), | ||
| SSP_CONFIG_DATA(SSP, 2, 16, 1, 0, 10))) |
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one last question: is the 16 here required? You are using 32 bits so you could send 24-bit data without issues. I don't know why the da7219 used 16 bits, but for cs42l42 you may want to revisit this.
This could be improved in a follow-up patch
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Add a topogy file for cs42l42 running on GLK boards. It's similar to da7219's
topology but we rearrange the id of backend DAI Links by moving speaker amp's
id (SSP1) to the end of links to reflect the machine driver changes from CML
platform.
We also add a 10 ms BCLK delay in this topology since the codec PLL is locking
on BCLK or there will be noise on TX path.
Signed-off-by: Brent Lu brent.lu@intel.com