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21 changes: 12 additions & 9 deletions sound/soc/sof/intel/hda-ctrl.c
Original file line number Diff line number Diff line change
Expand Up @@ -164,6 +164,9 @@ int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
{
struct hdac_bus *bus = sof_to_bus(sdev);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
struct hdac_ext_link *hlink;
#endif
struct hdac_stream *stream;
int sd_offset, ret = 0;

Expand All @@ -173,11 +176,6 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
hda_dsp_ctrl_misc_clock_gating(sdev, false);

if (full_reset) {
/* clear WAKESTS */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
SOF_HDA_WAKESTS_INT_MASK,
SOF_HDA_WAKESTS_INT_MASK);

/* reset HDA controller */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
Expand Down Expand Up @@ -245,13 +243,18 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* program the position buffer */
if (bus->use_posbuf && bus->posbuf.addr) {
snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
snd_hdac_chip_writel(bus, DPUBASE,
upper_32_bits(bus->posbuf.addr));
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
(u32)bus->posbuf.addr);
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
upper_32_bits(bus->posbuf.addr));
}

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* Reset stream-to-link mapping */
list_for_each_entry(hlink, &bus->hlink_list, list)
bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
#endif

bus->chip_init = true;
Expand Down
36 changes: 2 additions & 34 deletions sound/soc/sof/intel/hda-dsp.c
Original file line number Diff line number Diff line change
Expand Up @@ -355,6 +355,7 @@ static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
/* read STATESTS before controller reset */
status = snd_hdac_chip_readw(bus, STATESTS);
}
#endif

/* reset and start hda controller */
ret = hda_dsp_ctrl_init_chip(sdev, true);
Expand All @@ -364,14 +365,7 @@ static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
return ret;
}

hda_dsp_ctrl_misc_clock_gating(sdev, false);

/* Reset stream-to-link mapping */
list_for_each_entry(hlink, &bus->hlink_list, list)
bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);

hda_dsp_ctrl_misc_clock_gating(sdev, true);

#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* check jack status based on controller status */
if (runtime_resume)
hda_codec_jack_check(sdev, status);
Expand All @@ -385,32 +379,6 @@ static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
/* check dma status and clean up CORB/RIRB buffers */
if (!bus->cmd_dma_state)
snd_hdac_bus_stop_cmd_io(bus);
#else

hda_dsp_ctrl_misc_clock_gating(sdev, false);

/* reset controller */
ret = hda_dsp_ctrl_link_reset(sdev, true);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to reset controller during resume\n");
return ret;
}

/* take controller out of reset */
ret = hda_dsp_ctrl_link_reset(sdev, false);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to ready controller during resume\n");
return ret;
}

/* enable hda bus irq */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);

hda_dsp_ctrl_misc_clock_gating(sdev, true);
#endif

/* enable ppcap interrupt */
Expand Down