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🌱 StrictDoc development update: Reduced capacity in Q4 2026 #3174

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@stanislaw

The StrictDoc core team is working at approximately 25-50% of its usual capacity until the end of 2026. Development, issue responses, and pull request reviews may take longer during this period.

Thank you for your contributions, bug reports, and patience. We will work through your issues and pull requests as time allows.

Activity

  1. changed the title [-]Bug: Opening a link with an anchor to a section does not in page scrolled to that section[/-] [+][REUSE ME][/+] on Sep 5, 2026
  2. changed the title [-][REUSE ME][/-] [+]Reduced development capacity in Q4 2026[/+] on Oct 18, 2026
  3. changed the title [-]Reduced development capacity in Q4 2026[/-] [+]🌱 StrictDoc development update: Reduced capacity in Q4 2026[/+] on Oct 18, 2026
  4. pinned this issue on Oct 18, 2026
  5. awschult002 commented on Oct 20, 2026

    @awschult002
    Contributor

    if allowed. i can help with some stuff. i dont have much time (arent we all busy); but i do pay for an AI subscription and would be happy to unleash it on these bug fixes and things. let me know the teams thoughts.

  6. stanislaw commented on Oct 22, 2026

    @stanislaw
    CollaboratorAuthor

    When it comes to bugs, they are in two categories: trivial and more advanced. If you see something that looks trivial to you, feel free to propose PRs. For more advanced things, they need some time from the developers to assess them and come up with a fix.

    If you have time and are willing to contribute, would you be open on working on adding new features? For example, do you by any chance have experience with Java, VHDL or Ada? I would say you could help us quite well if you implemented the language support for one or more of these, similar to how the existing C/C++/Python/Rust are implemented. AI should be quite good at parsing and following the existing language readers that we already have.

  7. awschult002 commented on Oct 22, 2026

    @awschult002
    Contributor

    Actually... I do vhdl and FPGA work. I already have some parser work done for a different project. I would love to help contribute

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