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Part of #5119 (era 1: OS/VS COBOL addressing). Register X56.

Design

BLL cells map onto the pointer lane (#5041 / X47) with IBM's own conversion as the mechanism. The conversion is in the CICS/MVS 2.1.2 Application Programmer's Reference, SC33-0512-1: "Base locator for linkage (BLL)", pp. 21-23; "Converting to VS COBOL II", p. 29; Figure 3, p. 26.

det/bll.py rewrites the program before either side reads it:

• The BLL cell list leaves LINKAGE. Its cells become USAGE POINTER items in WORKING-STORAGE; the FILLER and the long record's secondary cells are dropped.
• SET(cell) stays SET(pointer).
• SERVICE RELOAD record becomes SET ADDRESS OF record TO cell, at the same place. IBM's timing is kept: the record is addressed anew only where the program reloads it.
• ADD 4096 cell GIVING next-cell is dropped.
• MOVE cell TO cell becomes SET cell TO cell.

The rewrite runs in two places:

• the det translator, in program._translate;
• the GnuCOBOL oracle, in equivalence_cics.translate.

So both sides run the same lowered program on the existing lane. No runtime changes: DetCics, CicsTask and ggcics.c are untouched.

Class table: constructs that address a LINKAGE record through a BLL cell

Member	Status
BLL list recognition: the first LINKAGE 01 after DFHCOMMAREA, FILLER first; one cell per 4096 bytes; evidence required	done here
GETMAIN SET(cell); FREEMAIN DATAPOINTER(cell)	done here (pointer lane)
SERVICE RELOAD record / list / DFHCOMMAREA; SERVICE RELOAD in a program with no cell list (VS COBOL II ignores it)	done here
Long records: ADD 4096 secondary cells reset before the reload	done here
MOVE cell TO cell + SERVICE RELOAD (IBM's p. 24 example)	done here
A cell changed with no reload before the paragraph ends (IBM's chained areas, re-addressed at the next paragraph name)	refused by name
A reload before the secondary cells are reset; a secondary cell set other than by ADD 4096; a cell used as a number or as data	refused by name
SERVICE LABEL (CICS translator output); SERVICE RELOAD of a non-LINKAGE item or of a record no cell addresses; DFHCOMMAREA after the list	refused by name
READ / READNEXT / READPREV / RECEIVE / RETRIEVE / READQ TS / LOAD SET(cell)	sibling gap: refused under their own reasons, as for a POINTER (#5042)
EXEC CICS ADDRESS CWA / TWA / TCTUA / EIB / CSA (cell)	sibling gap: refused under ADDRESS's whole-command reason

Every refusal reads "OS/VS COBOL BLL addressing: …: not modelled". They are mapped in refusal_map.json as bll-cells, so the support matrix names them.

Evidence

• tests/cobol_mainframe/test_bll_cells_5119.py:
  • IBM's examples lower as the manual converts them: Figure 3's long record, the p. 24 SERVICE RELOAD and MOVE examples, Figure 5's GETMAIN.
  • A program with no BLL evidence is left unchanged.
  • 12 refusals are each named.
  • The det translation has no holes.
  • The oracle's translate() lowers the same program.
  • EQUIVALENCE_E2E: a synthetic estate is proven against GnuCOBOL. It has a 5400-byte record over two cells, written past byte 4096 and aliased by a second record through MOVE cell TO cell. Both sides SEND the hand-traced HEAD******TAIL-BYTES.
• No corpus program uses BLL cells. The corpus cases are estate-crucible estate-crucible: era profiles -- era-tagged horrors with release-specific IBM citations, mixed-era strata, per-era scores #5118 S4–S6, per the owner's decision on det/CICS: BLL cells and SERVICE RELOAD (OS/VS COBOL addressing, era 1) #5119.

Gates (local)

• pr_gates --fast: 6/6 pass. pr_gates --ratchets: 7/7 pass (cics-spec, ports, port-surface, estate, fact-crosscheck, completeness, ground-truth).
• det_port.py check against origin/main: 112/112 ports unchanged, so no re-proof is needed.
• ruff_audit / mypy_audit --ci: no new findings.
• The related suites pass: test_det_translate, test_equivalence_cics, test_pointer_lane_4771, test_support_matrix, test_generated_docs, test_det_source_4462, test_det_osvs and test_det_programs.
• Golden masters: not run. The change is in the det translator and the equivalence harness, not the scan engine.

Cross-repo

None. Expect a refusal_map.json conflict with #5121, which also adds an entry; merge main if it lands first.

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