Don't require AVX512 for 128/256-bit GFNI & VPCLMULQDQ intrinsics

[Amanieu]

Fixes #1325

[rust-highfive]

@Amanieu: no appropriate reviewer found, use r? to override

[calebzulawski]

I think this requires a bit more changes to each individual intrinsic, including the EVEX ones. For example, from the Software Developer's Manual:

Note that the 512-bit EVEX-encoded instructions only require AVX512F, but the smaller width EVEX instructions require AVX512VL (and neither require AVX512BW, which is what the intrinsics currently require). VAES and VPCLMULQDQ have similar requirements.

[Amanieu]

I left the EVEX-encoded 128/256-bit variant as they were ("avx512gfni,avx512bw,avx512vl").

The AVX512BW requirement comes from LLVM, which will refuse to emit the correct instruction if we don't add that target feature.

[calebzulawski]

That's unfortunate, sure enough I see the same issue. I actually see an ICE when removing it. Do you know if there's an issue reported to LLVM?

[calebzulawski]

I opened llvm/llvm-project#58687