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    • The SoC for the introduction to chip design course spring 2026
      Scala
      Apache License 2.0
      2500Updated Apr 30, 2026Apr 30, 2026
    • Introduction to Chip Design
      Scala
      Other
      75600Updated Apr 21, 2026Apr 21, 2026
    • Introduction to Chip Design
      TeX
      1600Updated Apr 20, 2026Apr 20, 2026
    • A starting point for integrating Chisel designs into the Caravel SoC
      Makefile
      Apache License 2.0
      0000Updated Mar 10, 2026Mar 10, 2026
    • Subsystem DTU test tapeout
      SystemVerilog
      Apache License 2.0
      1300Updated Dec 1, 2025Dec 1, 2025
    • DTU chips project on caravel
      Verilog
      Apache License 2.0
      0100Updated Jun 6, 2025Jun 6, 2025
    • The SoC for the chip design course 2025
      Verilog
      BSD 2-Clause "Simplified" License
      2900Updated May 7, 2025May 7, 2025
    • Verilog
      Apache License 2.0
      0000Updated Nov 25, 2022Nov 25, 2022
    • TeX
      BSD 2-Clause "Simplified" License
      12400Updated Oct 24, 2022Oct 24, 2022
    • patmos-chip

      Public template
      https://caravel-user-project.readthedocs.io
      Verilog
      Apache License 2.0
      372100Updated Jun 16, 2022Jun 16, 2022
    • patmos

      Public
      Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
      VHDL
      BSD 2-Clause "Simplified" License
      74300Updated Jun 3, 2022Jun 3, 2022
    • ChipDay

      Public
      DTU Chip Day
      1600Updated Apr 26, 2022Apr 26, 2022
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