[SamuelRiedel]

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
7a4697f578c67c550fcad5e5e3078415e1f088d7

• [rtl,cheriot] Qualify CheriotWaddrMSBClear assertion with we_a_i (Samuel Riedel)
• [doc] Describe dummy instruction side effects (Kulan Palanichamy)
• [dv] Add dummy-instruction directed tests (Kulan Palanichamy)
• [dv] Add a single-step test with dummies armed (Kulan Palanichamy)
• [rtl] Keep dummy instructions out of Zcmp sequences (Kulan Palanichamy)
• [rtl] Exclude dummy instructions from minstret (Kulan Palanichamy)
• [rtl] Do not count a dummy instruction as a step (Kulan Palanichamy)
• [doc] Fix the icache data ECC layout (Andreas Kurth)
• [dv] Hold debug_req until the hart has halted (Kulan Palanichamy)
• [dv] Restrict single-step test CSR writes (Kulan Palanichamy)
• [vendor] Make the kernel-stack claim atomic (Kulan Palanichamy)
• [vendor] Pop the debug frame on debug exceptions (Kulan Palanichamy)
• [dv] Pop the trap frame in the ECALL handler (Kulan Palanichamy)
• [dv/cosim] Sample debug mode before the step (Kulan Palanichamy)
• [dv] Add zcmp_reserved_test (Kulan Palanichamy)
• [rtl] Keep a reserved Zcmp rlist trap unexpanded (Kulan Palanichamy)
• [rtl] Reject the reserved cm.mvsa01 encoding (Kulan Palanichamy)
• [dv] Sort directory listings in gen_testlist.py (Kulan Palanichamy)
• [dv] Accept a test once in filter_tests_by_config (Kulan Palanichamy)
• [dv] Add sim_opts to the directed-test schema (Kulan Palanichamy)
• [dv] Include CHERIoT Load/Store/Jump signals in fcov assertions (Samuel Riedel)
• [dv] Use the TweakInfection name in the icache TB (Kulan Palanichamy)

Unblocks #31644

[thommythomaso]

Thanks @SamuelRiedel. LGTM.

[andreaskurth]

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_compressed_decoder.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_dummy_instr.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv

Upstream Ibex fixes for dummy instructions (no single-step completion, no minstret increment, no insertion inside Zcmp sequences) and for reserved Zcmp encodings (cm.mvsa01 with r1s' == r2s', reserved push/pop rlist), plus new assertions.

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv

Assertion-only change: CheriotWaddrMSBClear is qualified with we_a_i.

[andreaskurth]

@nasahlpa Could you please review and authorize changes if you agree? There are more Ibex improvements to be vendored in for M3, but these are already important for M2. TIA!

[andreaskurth]

LGTM, thanks @SamuelRiedel!

[nasahlpa]

Thanks for updating Ibex. Some of the changes I already review in the Ibex repo.

[nasahlpa]

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_compressed_decoder.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_dummy_instr.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_if_stage.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_wb_stage.sv

Upstream Ibex fixes for dummy instructions (no single-step completion, no minstret increment, no insertion inside Zcmp sequences) and for reserved Zcmp encodings (cm.mvsa01 with r1s' == r2s', reserved push/pop rlist), plus new assertions.

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_latch.sv

Assertion-only change: CheriotWaddrMSBClear is qualified with we_a_i.