Repository navigation
Conversation
When an invalidate arrived while the icache was already waiting for a scrambling key, the testbench fetched a second key. That fetch could land in the middle of the icache's invalidation sweep. The RAMs reject writes while a key is being fetched, so some tags were not cleared and later read back as ECC errors. Fetch a key only when the icache asks for one, as ibex_top does. Signed-off-by: Kulan Palanichamy <kulan.palanichamy@opentitan.org>
The ECC assertions in the RAM interface passed rst_n where ASSERT expects an active-high reset, so they were off while the icache ran. Pass !rst_n. The icache checks data ECC only in the way that hit, so expect a data error only when the single way that hit is corrupted. A corrupted tag still gives an error on every lookup. A new check allows no error that the testbench did not inject. Data errors in a line held in two ways stay unchecked. Declare the read data as inputs of the unused clocking block. Signed-off-by: Kulan Palanichamy <kulan.palanichamy@opentitan.org>
The same line can be allocated to two icache ways. On a lookup that hits both, the icache ORed their data before the ECC check. A clean copy could then hide an error in the other copy, and two corrupted copies could merge into a valid codeword with a wrong instruction. Read only the lowest matching way, so the checked data is one way's data, as on a normal hit. A data error still invalidates every matching way. Update icache.rst to match. Signed-off-by: Kulan Palanichamy <kulan.palanichamy@opentitan.org>
DataErrChk_A skipped lookups that hit in more than one way. Require an error when the lowest matching way has an injected data error, and cover that case. Add ecc_back_line: back_line with more ECC errors, so that they land on lines held in two ways. It starts with an invalidation to vary the memory seed, since the initial seed makes fetches near address zero fail. It restores the settings it changes, also when it is killed. Add it to the stress sequences and the smoke regression. Signed-off-by: Kulan Palanichamy <kulan.palanichamy@opentitan.org>
SamuelRiedel
self-requested a review
October 7, 2026 14:30
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Without the RTL change in this PR, the new
ecc_back_linetest fails on most of the tested seeds:The icache can hold the same line in two ways when the core branches into a line that is still being fetched. A
lookup that hits both ways ORs their data before the ECC check. A clean copy can then hide corruption in the other
copy. Two corrupted copies can also merge into a valid codeword for a wrong instruction, which is returned without
an error.
This PR reads only the lowest matching way, so the ECC check sees one copy. A data error still invalidates every
matching way. Data in the other ways is not checked, as already happens for ways that miss.
I saw no material area change in a Yosys synthesis of
ibex_corewith theopentitanconfig. The added selectionlogic was off the critical path in that run, which excludes the register file and the lockstep copy.
The testbench now requires an error when the selected way holds injected data corruption. The new sequence
exercises this on duplicate hits.
Depends on #2515. The first two commits are from that PR.
I ran all icache tests through dvsim on VCS U-2023.03-SP2 with the default testbench parameters and random seeds.
All passed except one
stress_all_with_resetrun, which hit the reset race fixed in #2516. The new test failed on17 of 20 seeds without the RTL change and passed on all 20 with it. Lint passed on the six CI configs. I did not
run Xcelium.
AI disclosure (CLA §9): written with help from Claude Code and reviewed with OpenAI Codex; I have reviewed and understood every change and take full responsibility for it.