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[dv/cosim] Pass internal NMI mtval to Spike - #2518

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riscv_mem_intg_error_test fails on master on a few seeds with a cosim mismatch:

UVM_FATAL ... ibex_cosim_scoreboard.sv(172) @ 32529700: ... Cosim mismatch Register write data mismatch to x28 DUT: 80013bd2 expected: 0

The failing instruction reads mtval in a trap handler. When a load or store fails its integrity check, Ibex
takes the internal NMI and writes the failing address to mtval. Spike takes the NMI at the same point, but
the cosim only tells it that the NMI happened, so Spike sets mtval to zero. In the failing seeds the access
also raises an access fault, and the NMI arrives on entry to the fault handler. mret from the NMI does not
restore mtval, so the fault handler reads the address on Ibex and zero in Spike.

This PR adds an RVFI output, rvfi_ext_nmi_int_mtval, that carries this address. It travels through the
RVFI pipeline with the existing rvfi_ext_nmi_int bit. Spike writes it to mtval when it takes the internal
NMI. When Spike does not take it, for example because an external NMI wins, the existing checks in
set_nmi_int() skip the write. The new output only exists in RVFI builds, so the design itself does not
change.

I tested on VCS with the opentitan config. On 50 seeds of the test, 7 fail on master with this mismatch and
none fail on this branch. Both trees run the same programs. The nested interrupt, memory error and arithmetic
tests also pass. Simple System cosim passes CI's tests on opentitan and small. I did not hit an external
and an internal NMI at the same time.

This PR does not depend on other PRs. It touches the same cosim files as #2324 and adds one line to two
blocks that #2324 realigns, so whichever lands second needs a small rebase.

AI disclosure (CLA §9): written with help from Claude Code and reviewed with OpenAI Codex; I have reviewed and understood every change and take full responsibility for it.

When a load or store fails its integrity check, Ibex takes the
internal NMI and writes the failing address to mtval. The cosim only
tells Spike that the NMI happened, so Spike sets mtval to zero. The
cosim then reports a mismatch when a handler reads mtval.

Add an RVFI output that carries the address, and have Spike write it
to mtval when it takes the internal NMI. The output only exists in
RVFI builds.

Signed-off-by: Kulan Palanichamy <kulan.palanichamy@opentitan.org>
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