Observed Behavior
The mip register documentation (https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cs-registers) states
"mip is a read-only register indicating pending interrupt requests. A particular bit in the register reads as one if the corresponding interrupt input signal is high and if the interrupt is enabled in the mie CSR."
Expected Behavior
In https://github.com/lowRISC/ibex/blob/master/rtl/ibex_cs_registers.sv:
assign mip.irq_fast = irq_fast_i;
and
csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast;
These statements show that mip is not gated by mie. This is in line with the discussion in #567.
From the issue/567 discussion it's clear that mip not being gated by mie is the expected behavior, so it's the documentation that needs to be updated.
Steps to reproduce the issue
My Environment
EDA tool and version:
Operating system:
Version of the Ibex source code:
Latest.
Observed Behavior
The mip register documentation (https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cs-registers) states
"mip is a read-only register indicating pending interrupt requests. A particular bit in the register reads as one if the corresponding interrupt input signal is high and if the interrupt is enabled in the mie CSR."
Expected Behavior
In https://github.com/lowRISC/ibex/blob/master/rtl/ibex_cs_registers.sv:
assign mip.irq_fast = irq_fast_i;and
csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast;These statements show that mip is not gated by mie. This is in line with the discussion in #567.
From the issue/567 discussion it's clear that mip not being gated by mie is the expected behavior, so it's the documentation that needs to be updated.
Steps to reproduce the issue
My Environment
EDA tool and version:
Operating system:
Version of the Ibex source code:
Latest.