[cheriot,doc] Document the register file configurations #2479

ibex_register_file_ff.sv carries a table of the physical register allocations for each combination of BaseIsa, DummyInstructions and RV32E, added in #2475. It is a useful overview but currently lives in one implementation's header comment, while ibex_register_file_fpga.sv and ibex_register_file_latch.sv implement the same scheme.

Move the table into the documentation and reference it from all three implementations. #2475 does not extend the docs, so this was deferred.

While moving it, the two BaseIsa == BaseIsaRV32IorCHERIoT + DummyInstructions == 1 rows can be merged: RV32E is don't-care there, since inside g_cheriot_rf it only gates the non-CHERIoT upper-bank write enables and the g_rf_shared0_x16 guard, never the flop count.

Context: #2475 (comment)