ARM: Handle vldrh and vstrh in stack access hooks

[arsenm]

This is to help avoid regressions in a future regalloc patch.

I do not see the vstrh case appear in tests. There also appear
to be other cases unhandled here, like LDRBi12.

[arsenm]

• ARM: Handle vldrh and vstrh in stack access hooks #120527 👈 (View in Graphite)
• main

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[llvmbot]

@llvm/pr-subscribers-backend-arm

Author: Matt Arsenault (arsenm)

Changes

This is to help avoid regressions in a future regalloc patch.

I do not see the vstrh case appear in tests. There also appear
to be other cases unhandled here, like LDRBi12.

---

Full diff: https://github.com/llvm/llvm-project/pull/120527.diff

1 Files Affected:

• (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+2)

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e6b37dd9161685..e3e2e83fd5c7eb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1330,6 +1330,7 @@ Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case ARM::tSTRspi:
   case ARM::VSTRD:
   case ARM::VSTRS:
+  case ARM::VSTRH:
   case ARM::VSTR_P0_off:
   case ARM::VSTR_FPSCR_NZCVQC_off:
   case ARM::MVE_VSTRWU32:
@@ -1588,6 +1589,7 @@ Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case ARM::tLDRspi:
   case ARM::VLDRD:
   case ARM::VLDRS:
+  case ARM::VLDRH:
   case ARM::VLDR_P0_off:
   case ARM::VLDR_FPSCR_NZCVQC_off:
   case ARM::MVE_VLDRWU32:

[ostannard]

LGTM