[Hexagon][DAG][FREEZE] Fix bug 117337

[iajbar]

Add support to lower "FREEZE a half(f16)" instruction on Hexagon.

[llvmbot]

@llvm/pr-subscribers-backend-hexagon

Author: Ikhlas Ajbar (iajbar)

Changes

Add support to lower "FREEZE a half(f16)" instruction on Hexagon.

---

Full diff: https://github.com/llvm/llvm-project/pull/119042.diff

2 Files Affected:

• (modified) llvm/lib/Target/Hexagon/HexagonISelLowering.h (+2)
• (added) llvm/test/CodeGen/Hexagon/fp16-promote.ll (+48)

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 3fd961f5a74623..4774eba6f4e037 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -363,6 +363,8 @@ class HexagonTargetLowering : public TargetLowering {
     return AtomicExpansionKind::LLSC;
   }
 
+  bool softPromoteHalfType() const override { return true; }
+
 private:
   void initializeHVXLowering();
   unsigned getPreferredHvxVectorAction(MVT VecTy) const;
diff --git a/llvm/test/CodeGen/Hexagon/fp16-promote.ll b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
new file mode 100755
index 00000000000000..ce5ae51955877d
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fp16-promote.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon  < %s | FileCheck %s
+
+define half @freeze_half_undef() nounwind {
+; CHECK-LABEL: freeze_half_undef:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:     r0 = #0
+; CHECK-NEXT:     allocframe(#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:     r0 = sfadd(r0,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %y1 = freeze half undef
+  %t1 = fadd half %y1, %y1
+  ret half %t1
+}
+
+define half @freeze_half_poison(half %maybe.poison) {
+; CHECK-LABEL: freeze_half_poison:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0:
+; CHECK-NEXT:    .cfi_def_cfa r30, 8
+; CHECK-NEXT:    .cfi_offset r31, -4
+; CHECK-NEXT:    .cfi_offset r30, -8
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __extendhfsf2
+; CHECK-NEXT:     allocframe(r29,#0):raw
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     call __truncsfhf2
+; CHECK-NEXT:     r0 = sfadd(r0,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r31:30 = dealloc_return(r30):raw
+; CHECK-NEXT:    }
+  %y1 = freeze half %maybe.poison
+  %t1 = fadd half %y1, %y1
+  ret half %t1
+}

[androm3da]

CodeGen/Hexagon/isel-buildvector-v2f16.ll fails with this change.

[alexrp]

On the Zig side we'd love to get this landed in time for LLVM 20 if possible. Anything I can do to help move this forward?

[androm3da]

I believe that this PR was obsoleted by #130977. Closing.