[AMDGPU][MC][GFX9] Several VOP3 opcodes do not support op_sel

[dpreobra]

Bugzilla Link	39302
Version	trunk
OS	All
CC	@atamazov,@arsenm

Extended Description

According with AMD docs, the following opcodes should support op_sel:

• v_alignbit_b32
• v_alignbyte_b32
• v_interp_p2_f16

Also there are 'legacy' opcodes:

• v_mad_legacy_f16
• v_mad_legacy_i16
• v_mad_legacy_u16
• v_fma_legacy_f16
• v_interp_p2_legacy_f16
• v_div_fixup_legacy_f16

These are labelled in SP3 as accepting op_sel; AMD docs says nothing about that. I believe these legacy opcodes should not support op_sel because this feature is not in GFX8.

[dpreobra]

assigned to @dpreobra

[jwanggit86]

As far as v_mad_legacy_* instructions are concerned, both MI100 and MI200 specs indicate at least op_sel[3] is used. So it seems op_sel should be supported in these cases.

[jwanggit86]

PR 149262 solves this issue for v_alignbit and v_alignbyte.

[jwanggit86]

PR 150712 solves this for v_interp_p2_f16.

[llvmbot]

@llvm/issue-subscribers-llvm-mc

Author: None (dpreobra)

Details

| | | | --- | --- | | Bugzilla Link | [39302](https://llvm.org/bz39302) | | Version | trunk | | OS | All | | CC | @atamazov,@arsenm |

Extended Description

According with AMD docs, the following opcodes should support op_sel:

• v_alignbit_b32
• v_alignbyte_b32
• v_interp_p2_f16

Also there are 'legacy' opcodes:

• v_mad_legacy_f16
• v_mad_legacy_i16
• v_mad_legacy_u16
• v_fma_legacy_f16
• v_interp_p2_legacy_f16
• v_div_fixup_legacy_f16

These are labelled in SP3 as accepting op_sel; AMD docs says nothing about that. I believe these legacy opcodes should not support op_sel because this feature is not in GFX8.