pcm-latency reports small latency

[majid0jalili]

Hi,
I was trying to measure the DRAM latency with pcm-latency, and I noticed that the number it reports is a bit off.
For example, I ran GUPS and STREAM and below is the output for one iteration, although it is roughly similar for other samples:
GUPS:
Average latency per socket
L1 Cache Miss Latency(ns) [Adding 5 clocks for L1 Miss]
Socket0: 4.97
Socket1: 5.10
DDR read Latency(ns)
Socket0: 27.27
Socket1: 27.22

STREAM
Average latency per socket
L1 Cache Miss Latency(ns) [Adding 5 clocks for L1 Miss]
Socket0: 21.26
Socket1: 21.40
DDR read Latency(ns)
Socket0: 118.13
Socket1: 106.93

There is no way this can be true; a fully random access pattern has that low latency. I digged further and used perf stat to see if this can be solved. I noticed perf stat uses 3 hw counters to measure latency
C1=cha/event=0x36\,umask=0x21\,config=0x40433/
C2=cha/event=0x35\,umask=0x21\,config=0x40433/
C3=cha_0/event=0x0/
Then, does C1/C2/C3*1billion to report the DRAM latency. I took the below from the Kernel website

"MetricExpr": "1000000000 * ( cbox@event\=0x36\,umask\=0x3\,filter_opc\=0x182@ / cbox@event\=0x35\,umask\=0x3\,filter_opc\=0x182@ ) / ( cbox_0@event\=0x0@ / duration_time )",
"BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
"MetricGroup": "Memory_Lat",
"MetricName": "DRAM_Read_Latency"

I tried on two different machines SKX and casecadelake and observe the same behavior.

[rdementi]

There are a few differences:

The DDR latency reported by pcm-latency is measured at the memory controller.
The CHA-based miss latency metrics is measured at LLC(CHA) and includes both the uncore (cache/mesh) latency + DDR latency.

The pcm main utility has LLCRDMISSLAT metric which is similar to the mentioned CHA miss latency.