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ci: fix Models Backend by shortening the hrm_text fixture - #29744
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The fixture recycles its two blocks over 8 cache slots, so the fp16 error builds up past the 1e-4 NMSE bound on the Vulkan T4 and WebGPU jobs of Models Backend. Two l-cycles keep every branch of the cycle loop and halve the error.
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Measured on an RTX PRO 6000, where the values differ from the CI GPUs, but the error scales with the depth so the CI should drop by the same ratio. The Models Backend run on this PR will confirm. |
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cc/ @jeffbolznv |
pierreguillot
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…l-org#29744) The fixture recycles its two blocks over 8 cache slots, so the fp16 error builds up past the 1e-4 NMSE bound on the Vulkan T4 and WebGPU jobs of Models Backend. Two l-cycles keep every branch of the cycle loop and halve the error.
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…l-org#29744) The fixture recycles its two blocks over 8 cache slots, so the fp16 error builds up past the 1e-4 NMSE bound on the Vulkan T4 and WebGPU jobs of Models Backend. Two l-cycles keep every branch of the cycle loop and halve the error.
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…l-org#29744) The fixture recycles its two blocks over 8 cache slots, so the fp16 error builds up past the 1e-4 NMSE bound on the Vulkan T4 and WebGPU jobs of Models Backend. Two l-cycles keep every branch of the cycle loop and halve the error. (cherry picked from commit 3b3d022)
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Overview
Fix CI:
The new Models Backend check is red on every run because of hrm_text: it lands just above the 1e-4 bound on Vulkan (1.10e-04) and WebGPU (1.53e-04), same numbers every time.
The bound is fine, the hrm_text test model is just too deep for it. HRM reuses its layers in cycles, and our fixture runs them through 8 passes where most archs have 2. Each pass adds a bit of fp16 rounding, so it ends up about 10x noisier than any other arch. With f16 disabled it drops to 3.5e-10, so nothing is wrong in the model itself.
This PR makes the fixture a bit shorter: 6 passes instead of 8. It still goes through every branch of the cycle loop, and the error roughly halves.
NMSE over 5 seeds on an RTX PRO 6000:
Additional information
Follow-up #29651 cc @CISC
Requirements