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metal: FWHT kernels for block widths above 512 - #29095

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ggerganov merged 2 commits into
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PrismML-Eng:up/fwht-metal-wide
Sep 25, 2026
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ggerganov merged 2 commits into
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PrismML-Eng:up/fwht-metal-wide

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Overview

The Metal FWHT covers block widths 64 to 512. It runs one row per simdgroup and keeps
N/32 values per lane, so wider blocks need more registers per lane than that layout
allows.

kernel_fwht_tg runs one row per threadgroup with 256 threads, so each thread keeps
N/256 values instead. Butterflies below the simdgroup width still shuffle, those up to
the threadgroup width go through threadgroup memory, and the rest stay in registers. The
butterfly and sign convention match the existing kernel.

Widths 64 to 512 keep the simdgroup kernel and are untouched. 1024 through 8192 use the
new one, for both F32 and F16 sources.

Additional information

Stacked on #29094, which adds the F16 source type. The last commit is the one to review here.

8192 allocates 32 KB of threadgroup memory, which is the limit on the devices I can test.
ggml_metal_fwht_supported_size stops there for that reason, and anything wider keeps the
existing behaviour of falling back to the generic matmul path.

Tested on an M5 Pro with test-backend-ops:

  • MUL_MAT_HADAMARD 26/26, including the new 1024/2048/4096/8192 cases in F32 and F16
  • MUL_MAT 1265/1265, no regressions

The previous "too big" test case moved from 1024 to 16384, since 1024 is now covered.

Requirements

  • I have read and agree with the contributing guidelines
  • AI usage disclosure: YES. Claude Code was used to write and test this change, following the
    structure of the existing simdgroup kernel, and to format this description to the PR template.
    I reviewed every line and take full responsibility for the changes.

@bri-prism
bri-prism requested review from a team and ggerganov as code owners September 18, 2026 18:14
@github-actions github-actions Bot added testing Everything test related ggml changes relating to the ggml tensor library for machine learning Apple Metal https://en.wikipedia.org/wiki/Metal_(API) labels Sep 18, 2026
@ggerganov ggerganov self-assigned this Sep 18, 2026
@bri-prism
bri-prism force-pushed the up/fwht-metal-wide branch 7 times, most recently from 13c2ed8 to b25c008 Compare September 19, 2026 18:09
The Metal FWHT covers widths 64 to 512, one row per simdgroup with N/32 values
per lane. Wider blocks need more registers per lane than that layout allows.

kernel_fwht_tg runs one row per threadgroup with 256 threads, so each thread
keeps N/256 values. Butterflies below the simdgroup width still shuffle, those
up to the threadgroup width go through threadgroup memory, and the rest stay in
registers. Same butterfly and sign convention as the simdgroup kernel.

Widths 64 to 512 keep the simdgroup kernel. 1024 through 8192 use the new one,
for both F32 and F16 sources.

The wide kernels allocate float[N] of threadgroup memory, 32 KB at 8192, so the
size check takes the device limit and reports those widths as unsupported where
they would not fit. Without that a device with less threadgroup memory would
accept the op and then abort on a nil pipeline.

test-backend-ops on M5 Pro: MUL_MAT_HADAMARD 26/26, MUL_MAT 1265/1265.
@bri-prism

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@ggerganov this one's reconciled and mergeable now, ready for another look whenever you have time.

Comment thread ggml/src/ggml-metal/kernels/misc.metal
@ggerganov
ggerganov merged commit e351231 into ggml-org:master Sep 25, 2026
1 check passed
feal87 added a commit to feal87/myllama.cpp that referenced this pull request Sep 25, 2026
Merge upstream commits:
  - llama: add llama_prec_policy + model-driven W4A4 path (ggml-org#24364)
  - llama: fix tensor split for fused qkv with uneven K/V head sizes (ggml-org#29294)
  - metal: split fa kernels into per-dtype libraries (ggml-org#29329)
  - metal: FWHT kernels for block widths above 512 (ggml-org#29095)
  - CUDA: fuse RMS_NORM + SCALE into one kernel (ggml-org#29393)
  - common: extract shared unicode path/string helpers (ggml-org#29415)
  - common,rpc: simplify fs_create_directory_with_parents() (ggml-org#29432)
  - rpc: include nb in the get_alloc_size cache key (ggml-org#29283)
  - [SYCL] support sparse FA (ggml-org#28796)
  - musa: fix PH1 operator failures and build issues (ggml-org#29193)
  - HIP: bump HIP_VERSION required for fp8 (ggml-org#29231)
  - opencl: add q5_k bin kernel (ggml-org#29401)
  - hexagon: add q5_k quant type support (ggml-org#29123)
  - hexagon: use DMA for contiguous dim1 CONCAT (ggml-org#29404)
  - mtmd: fix mel preprocessor in LFM2 audio (ggml-org#29403)
  - vulkan: fix legacy GLSLC without cooperativeMatrix (ggml-org#29409)
  - gguf-py: ByteLevel processing defaults bos/eos to False (ggml-org#29422)
  - gguf-py: TemplateProcessing has final word on add_special_token (ggml-org#29417)

Assisted-by: Pi
sky-mighty pushed a commit to sky-mighty/llama.cpp that referenced this pull request Sep 26, 2026
* metal: FWHT kernels for block widths above 512

The Metal FWHT covers widths 64 to 512, one row per simdgroup with N/32 values
per lane. Wider blocks need more registers per lane than that layout allows.

kernel_fwht_tg runs one row per threadgroup with 256 threads, so each thread
keeps N/256 values. Butterflies below the simdgroup width still shuffle, those
up to the threadgroup width go through threadgroup memory, and the rest stay in
registers. Same butterfly and sign convention as the simdgroup kernel.

Widths 64 to 512 keep the simdgroup kernel. 1024 through 8192 use the new one,
for both F32 and F16 sources.

The wide kernels allocate float[N] of threadgroup memory, 32 KB at 8192, so the
size check takes the device limit and reports those widths as unsupported where
they would not fit. Without that a device with less threadgroup memory would
accept the op and then abort on a nil pipeline.

test-backend-ops on M5 Pro: MUL_MAT_HADAMARD 26/26, MUL_MAT 1265/1265.

* cont : add TODOs

---------

Co-authored-by: Georgi Gerganov <ggerganov@gmail.com>
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