Implement StreamBuffer modules#15
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- wip: implemented stream cache writer, working on reader - implement stream reader - add tests for stream cache - move from stream cache to buffer, change semantics - use a reset state to prevent mem_config_i swallowing in StreamWriter - clarify unit test names - remove old needless edits - tie off other card signals if any
JonasDann
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Apr 22, 2026
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The StreamBufferReader needs a config to be able to replay the same data multiple times.
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My idea for this was just that the link instead of being piped directly from the writer to the reader, would go through by a middleman component. There we decide what to have the reader read, and if repeatedly, how many times, and such.
But that's conceptually logic that belongs to another module IMO.
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Ah, fair enough. That makes sense. Let me try out the stuff and then I will merge it. We need it fairly soon.
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These modules allow you to write and (immediately) retrieve data to/from the FPGA's HBM.
The Reader and Writer modules are interconnected with a "link" that notifies the reader of when new data has been fully flushed to the HBM by the writer. This is designed such that a middleware can be placed in between the reader and writer to get the reader to read only parts of the written memory.
Included in this PR is a minor generalization of the StreamWriter and a small bugfix:
mem_config.buffer_readysignal to low when the StreamWriter is resetting, by way of adding a new RESET state to the StreamWriter state machine. This prevents discarding potential databeats while the module is being reset (this can happen, as there are delays added by the reset resync logic).