RISC-V: Optimize crc32c with Zbc extension

[fengpengboa]

This PR introduces optimized CRC32C hardware acceleration for RISC-V platforms that support the Zbc (Carry-less Multiplication) extension. The implementation leverages the clmul instruction to compute CRC32C more efficiently, providing significant performance improvements over the existing software-based fallback.

1.crc32c test
[==========] Running 8 tests from 1 test case.
[----------] Global test environment set-up.
[----------] 8 tests from CRC
[ RUN ] CRC.StandardResults
[ OK ] CRC.StandardResults (2 ms)
[ RUN ] CRC.Values
[ OK ] CRC.Values (0 ms)
[ RUN ] CRC.Extend
[ OK ] CRC.Extend (0 ms)
[ RUN ] CRC.Mask
[ OK ] CRC.Mask (0 ms)
[ RUN ] CRC.Crc32cCombineBasicTest
[ OK ] CRC.Crc32cCombineBasicTest (0 ms)
[ RUN ] CRC.Crc32cCombineOrderMattersTest
[ OK ] CRC.Crc32cCombineOrderMattersTest (0 ms)
[ RUN ] CRC.Crc32cCombineFullCoverTest
[ OK ] CRC.Crc32cCombineFullCoverTest (70 ms)
[ RUN ] CRC.Crc32cCombineBigSizeTest
[ OK ] CRC.Crc32cCombineBigSizeTest (151 ms)
[----------] 8 tests from CRC (225 ms total)

[----------] Global test environment tear-down
[==========] 8 tests from 1 test case ran. (225 ms total)
[ PASSED ] 8 tests.

2.Performance Results
Performance was measured using the crc32c_bench microbenchmark on a SG2044.
./db_bench --benchmarks="crc32c"

Software fallback : 10.396 micros/op 96189 ops/sec 13.307 seconds 1280000 operations; 375.7 MB/s (4096 per op)
zbc optimized : 0.617 micros/op 1621320 ops/sec 0.789 seconds 1280000 operations; 6333.3 MB/s (4096 per op)

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