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                               Copyright 2015-2024 / EnjoyDigital

                           A small footprint and configurable Logic Analyzer
                                    core powered by Migen & LiteX

[> Intro

LiteScope provides a small footprint and configurable embedded logic analyzer that you can use in your FPGA and aims to provide a free, portable and flexible alternative to vendor's solutions!

LiteScope is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteScope can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

• IO peek and poke with LiteScopeIO.
• Logic analyser with LiteScopeAnalyzer:
  • Subsampling.
  • Data storage in Block RAM.
  • Configurable triggers.
  • Optional run-length encoding (RLE) for repeated samples.
• Bridges:
  • UART <--> Wishbone (provided by LiteX)
  • Ethernet <--> Wishbone ("Etherbone") (provided by LiteEth)
  • PCIe <--> Wishbone (provided by LitePCIe)
• Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...

[> Run-Length Encoding

LiteScopeAnalyzer can optionally compress repeated samples before storing them:

analyzer = LiteScopeAnalyzer(
    signals,
    depth      = 1024,
    with_rle   = True,
    rle_length = 256,
)

RLE is disabled by default. With the default with_rle=False, the analyzer datapath and storage width remain the same as a non-RLE analyzer, so existing designs keep the normal raw capture behavior.

When RLE is enabled at build time, software can enable it for a capture:

analyzer = LiteScopeAnalyzerDriver(bus.regs, "analyzer", config_csv="analyzer.csv")
analyzer.configure_rle(True)

The encoder stores raw samples and repeat-count words. The stored word MSB is used as the RLE marker bit: marker 0 is a raw sample, marker 1 repeats the previous sample by the encoded count. The driver expands RLE captures back to normal DumpData, so dump/export users see logical samples.

Compression depends on signal activity:

• No repeated samples: no word-count compression; this is the worst case.
• A run of N identical samples stores as: 1 + ceil((N - 1) / (rle_length - 1)) encoded words.
• With rle_length=256, a stable 256-sample run stores in 2 words, and a stable 1024-sample run stores in 6 words.

With RLE enabled, depth and capture length describe encoded storage words, not final decoded sample count. A compressed capture can therefore decode to more logical samples than the configured storage length. To cap the decoded logical samples returned by the driver:

data = analyzer.upload(max_samples=1024)

[> Proven

LiteScope has already been used to investigate issues on several commercial or open-source designs.

[> Possible improvements

• add standardized interfaces (AXI, Avalon-ST)
• add protocols analyzers
• add signals injection/generation
• add storage in DRAM
• add storage in HDD with LiteSATA core
• add representative FPGA timing checks for optional analyzer features such as RLE
• add more simulation transports to CI, such as Etherbone in addition to the virtual UART path
• ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.

[> Getting started

1. Install Python 3.6+ and FPGA vendor's development tools.
2. Install LiteX and the cores by following the LiteX's wiki installation guide.
3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.

[> Tests

Unit and simulation tests are available in ./test/. To run the full test suite:

$ python3 -m pytest -q

Tests can also be run individually:

$ python3 -m pytest -q test/test_driver.py

The CI suite includes a litex_sim/Verilator end-to-end test that instantiates LiteScopeAnalyzer, controls it through a simulated LiteX UART BIOS console, and uploads captures through LiteScopeAnalyzerDriver. This covers both normal raw captures and RLE captures in simulation.

[> License

LiteScope is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteScope for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

• tell us that you are using LiteScope
• cite LiteScope in publications related to research it has helped
• send us feedback and suggestions for improvements
• send us bug reports when something goes wrong
• send us the modifications and improvements you have done to LiteScope.

[> Support and consulting

We love open-source hardware and like sharing our designs with others.

LiteScope is developed and maintained by EnjoyDigital.

If you would like to know more about LiteScope or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :)

[> Contact

E-mail: florent [AT] enjoy-digital.fr