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Refactoring GenTreeVecCon to support TYP_SIMD64 #83053

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Merged
tannergooding merged 4 commits into from
Mar 8, 2023
Merged

Refactoring GenTreeVecCon to support TYP_SIMD64 #83053

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a0f05fb
Refactoring GenTreeVecCon to support TYP_SIMD64
tannergooding Mar 6, 2023
b7fa68a
Apply formatting patch
tannergooding Mar 7, 2023
29edda2
Fixing a couple bugs in the refactoring
tannergooding Mar 7, 2023
bedcca1
Respond to some PR feedback by deduplicating code
tannergooding Mar 8, 2023
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20 changes: 15 additions & 5 deletions src/coreclr/jit/assertionprop.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3192,7 +3192,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
simd8_t value = vnStore->ConstantValue<simd8_t>(vnCns);

GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet());
vecCon->gtSimd8Val = value;
memcpy(&vecCon->gtSimdVal, &value, sizeof(simd8_t));

conValTree = vecCon;
break;
Expand All @@ -3203,7 +3203,7 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
simd12_t value = vnStore->ConstantValue<simd12_t>(vnCns);

GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet());
vecCon->gtSimd12Val = value;
memcpy(&vecCon->gtSimdVal, &value, sizeof(simd12_t));

conValTree = vecCon;
break;
Expand All @@ -3214,20 +3214,30 @@ GenTree* Compiler::optVNConstantPropOnTree(BasicBlock* block, GenTree* tree)
simd16_t value = vnStore->ConstantValue<simd16_t>(vnCns);

GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet());
vecCon->gtSimd16Val = value;
memcpy(&vecCon->gtSimdVal, &value, sizeof(simd16_t));

conValTree = vecCon;
break;
}

#if defined(TARGET_XARCH)
case TYP_SIMD32:
case TYP_SIMD64: // TODO-XArch-AVX512: Fix once GenTreeVecCon supports gtSimd64Val.
{
simd32_t value = vnStore->ConstantValue<simd32_t>(vnCns);

GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet());
vecCon->gtSimd32Val = value;
memcpy(&vecCon->gtSimdVal, &value, sizeof(simd32_t));

conValTree = vecCon;
break;
}

case TYP_SIMD64:
{
simd64_t value = vnStore->ConstantValue<simd64_t>(vnCns);

GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet());
memcpy(&vecCon->gtSimdVal, &value, sizeof(simd64_t));

conValTree = vecCon;
break;
Expand Down
35 changes: 27 additions & 8 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2388,16 +2388,16 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
// Get a temp integer register to compute long address.
regNumber addrReg = tree->GetSingleTempReg();

simd8_t constValue = vecCon->gtSimd8Val;
CORINFO_FIELD_HANDLE hnd = emit->emitSimd8Const(constValue);
simd8_t constValue;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd8_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd8Const(constValue);
emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0);
}
break;
}

case TYP_SIMD12:
case TYP_SIMD16:
{
if (vecCon->IsAllBitsSet())
{
Expand All @@ -2413,14 +2413,33 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
regNumber addrReg = tree->GetSingleTempReg();

simd16_t constValue = {};

if (vecCon->TypeIs(TYP_SIMD12))
memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t));
else
constValue = vecCon->gtSimd16Val;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd12_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue);
emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0);
}
break;
}

case TYP_SIMD16:
{
if (vecCon->IsAllBitsSet())
{
emit->emitIns_R_I(INS_mvni, attr, targetReg, 0, INS_OPTS_4S);
}
else if (vecCon->IsZero())
{
emit->emitIns_R_I(INS_movi, attr, targetReg, 0, INS_OPTS_4S);
}
else
{
// Get a temp integer register to compute long address.
regNumber addrReg = tree->GetSingleTempReg();

simd16_t constValue;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd16_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue);
emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0);
}
break;
Expand Down
32 changes: 18 additions & 14 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -550,46 +550,50 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
#if defined(FEATURE_SIMD)
case TYP_SIMD8:
{
simd8_t constValue = vecCon->gtSimd8Val;
CORINFO_FIELD_HANDLE hnd = emit->emitSimd8Const(constValue);
simd8_t constValue;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd8_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd8Const(constValue);
emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0);
break;
}

case TYP_SIMD12:
case TYP_SIMD16:
{
simd16_t constValue = {};

if (vecCon->TypeIs(TYP_SIMD12))
memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t));
else
constValue = vecCon->gtSimd16Val;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd12_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue);
emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0);
break;
}

case TYP_SIMD16:
{
simd16_t constValue;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd16_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue);
emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0);
break;
}

case TYP_SIMD32:
{
simd32_t constValue = vecCon->gtSimd32Val;
CORINFO_FIELD_HANDLE hnd = emit->emitSimd32Const(constValue);
simd32_t constValue;
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd32_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd32Const(constValue);
emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0);
break;
}

case TYP_SIMD64:
{
simd64_t constValue;
// TODO-XArch-AVX512: Fix once GenTreeVecCon supports gtSimd64Val.
constValue.v256[0] = vecCon->gtSimd32Val;
constValue.v256[1] = vecCon->gtSimd32Val;
CORINFO_FIELD_HANDLE hnd = emit->emitSimd64Const(constValue);
memcpy(&constValue, &vecCon->gtSimdVal, sizeof(simd64_t));

CORINFO_FIELD_HANDLE hnd = emit->emitSimd64Const(constValue);
emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0);
break;
}
Expand Down
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