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DispatchResolve: Avoid clobbering t1 in RhpInterfaceDispatch - #132134

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maximmenshikov:fix/dispatch
Aug 12, 2026
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jkotas merged 1 commit into
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maximmenshikov:fix/dispatch

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@maximmenshikov

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The tail pseudo-instruction expands to auipc t1 + jalr t1, which destroys the dispatch cell address just placed in t1 as the thunk target's parameter. Perform the tail jump manually through t2 instead, matching what RhpInterfaceDispatchSlow does in StubDispatch.S.

The `tail` pseudo-instruction expands to auipc t1 + jalr t1, which destroys the
dispatch cell address just placed in t1 as the thunk target's parameter. Perform
the tail jump manually through t2 instead, matching what
RhpInterfaceDispatchSlow does in StubDispatch.S.

Signed-off-by: Maxim Menshikov <maksim.menshikov@nethermind.io>
@dotnet-policy-service dotnet-policy-service Bot added the community-contribution Indicates that the PR has been added by a community member label Aug 11, 2026
@maximmenshikov

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@am11 @filipnavara could you take a look?

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@maximmenshikov

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similar to this PR:
#128374

Comment thread src/coreclr/nativeaot/Runtime/riscv64/DispatchResolve.S
@jkotas jkotas added the arch-riscv Related to the RISC-V architecture label Aug 12, 2026
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jkotas merged commit 19a2d97 into dotnet:main Aug 12, 2026
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