Arm64 RyuJIT: Lower/Codegen can take advantage of ability to reserve an internal register different from target without requiring to reserve two registers

[sivarv]

Lower/Codegen changes are done for xarch along with LSRA support.
Now Lower needs to set gtLsraInfo.isInternalRegDelayFree on a node to request an internal register different from its targetReg.

Note that isInternalRegDelayFree is not required to be set if the node produces no result in a reg or if it produces a result in an integer register and reserving floating-point type registers or vice versa.

[briansull]

xarch implementation:

Support Lower to reserve internal register(s) different from targetReg. dotnet/coreclr#7285

[CarolEidt]

@sdmaclea - I believe that arm64 is already setting delayFree where it is required. Can you confirm that (so we can close this), or point to where it should be done and isn't?

[sdmaclea]

@CarolEidt I also think this can be closed. I am not aware of any place where this is wrong. However, there are a few JitStress and JitStressReg failures which might indicate a defect. See dotnet/coreclr#16359 dotnet/coreclr#17111 dotnet/coreclr#17861

[CarolEidt]

@sdmaclea - thanks. I'll close this and we can address those issues separately.