[Arm64] Detect and emit right addressing mode for Load and Store intrinsics

[echesakov]

See the discussion after this question

#33532 (comment)

@TamarChristinaArm
Question about these store intrinsics in general, how are you guys planning on dealing with the different addressing modes? or are you only interested in a the register addressing modes?

cc @CarolEidt @TamarChristinaArm @tannergooding

category:cq
theme:hardware-intrinsics
skill-level:intermediate
cost:medium

[tannergooding]

Do we have some existing support for this in codegen/emitter? I would guess we have some support for the non-vector code paths already...

[echesakov]

Do we have some existing support for this in codegen/emitter? I would guess we have some support for the non-vector code paths already...

You mean support for emitting an instruction with post-index addressing mode?

[tannergooding]

Yes, like does the JIT already support this for array indexing, etc?

[echesakov]

Support for emitting all possible variants of ld1, st1 was added in #33461 - this includes post-indexing variants as well.

However, the actual optimization is a harder problem and I don't think we are doing this for array indexing at the moment. (see also my comment here #33532 (comment))

[CarolEidt]

I don't believe we do any post-increment optimizations in the JIT.

[echesakov]

I copied below a part of the @TamarChristinaArm's reply in #33749 (comment) that demonstrates how the optimization could potentially improve codegen

e.g. this code for And

G_M9258_IG18:
        93407CC9          sxtw    x9, w6
        D37EF529          lsl     x9, x9, #2
        8B0900EA          add     x10, x7, x9
        4C407950          ld1     {v16.4s}, [x10]
        8B090109          add     x9, x8, x9
        4C407931          ld1     {v17.4s}, [x9]
        4E311E10          and     v16.4s, v16.4s, v17.4s
        4C007950          st1     {v16.4s}, [x10]
        110010C6          add     w6, w6, #4
						;; bbWeight=2    PerfScore 21.00
G_M9258_IG19:
        51000CA9          sub     w9, w5, #3
        6B0900DF          cmp     w6, w9
        54FFFEAB          blt     G_M9258_IG18

should ideally be

G_M9258_IG18:
        93407CC9          sxtw    x9, w6
        D37EF529          lsl     x9, x9, #2
        4C407950          ldr     q16, [x7, x9]
        4C407931          ldr     q17, [x8, x9]
        4E311E10          and     v16.4s, v16.4s, v17.4s
        4C007950          str     q16, [x7, x9]
        110010C6          add     w6, w6, #4
						;; bbWeight=2    PerfScore 21.00
G_M9258_IG19:
        51000CA9          sub     w9, w5, #3
        6B0900DF          cmp     w6, w9
        54FFFEAB          blt     G_M9258_IG18

Which means you don't need the adjustment for x7 and x8.
The writeback would work for the single use case (rightPtr) but
the multi-use cases become tricky as you have to do the writeback only once.