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[wasm][R2R] crossgen2 aborts compiling HardwareIntrinsics General Vector128_1 tests for browser-wasm #134976
In the browser-wasm R2R_CG2 runtime-test lane, crossgen2 aborts (exit code 134, core dumped) while compiling Vector128_1_r.dll and Vector128_1_ro.dll from JIT/HardwareIntrinsics/General/Vector128_1. Nothing is written to stdout or stderr before the abort:
Running CrossGen2: .../crossgen2/crossgen2 @.../HardwareIntrinsics_General_r/Vector128_1_r.wasm.rsp -r:.../HardwareIntrinsics_General_r/IL-CG2/*.dll -f wasm
[createdump] The app model does not support crash report generation
[createdump] Failure took 0ms
[createdump] Target process is alive
JIT/HardwareIntrinsics/HardwareIntrinsics_General_r/HardwareIntrinsics_General_r.sh: line 258: 300 Aborted (core dumped) $__Command
Crossgen2 failed with exitcode: 134
The merged runner stops at the first crossgen2 failure, so no test in HardwareIntrinsics_General_r or HardwareIntrinsics_General_ro runs under R2R. The assemblies compiled before this one (NotSupported_r, ScalarConstantFoldings, SimdConstantFoldings, TestLibrary) succeeded. It is not yet known whether the remaining Vector* assemblies compile.
Both runners pass in the browser-wasm interpreter leg.
A core dump (core.1000.300) is uploaded to the HardwareIntrinsics_General_r work item.
Local investigation
Reproduced locally with a browser-wasm Checked build (osx-arm64 host crossgen2). With Vector128_1_* excluded, crossgen2 next fails on Vector128_r.dll. On macOS it does not abort; several JIT worker threads spin at the same place:
lower.cpp:5661 is the return LowerStoreLocCommon(lclStore); after SpillStructCallResult, on the path for a struct call result that has a single return register and can't be retyped to a primitive. The fault there is re-dispatched over and over. On Linux Helix the same fault shows up as the exit-134 abort above.
Because more than one assembly in the runner is affected, the quarantine turns off ReadyToRun for the HardwareIntrinsics_General_r/_ro runners on wasm CoreCLR. Their interpreter coverage is kept.
Configuration
browser-wasm, CoreCLR, Checked, R2R_CG2 (crossgen2 at Helix time), Linux x64 host
Description
In the browser-wasm
R2R_CG2runtime-test lane, crossgen2 aborts (exit code 134, core dumped) while compilingVector128_1_r.dllandVector128_1_ro.dllfromJIT/HardwareIntrinsics/General/Vector128_1. Nothing is written to stdout or stderr before the abort:crossgen2 options:
-O --targetarch:wasm --targetos:browser --verify-type-and-field-layout --method-layout:random --codegenopt:JitWasmNyiToR2RUnsupported=1 --verify-gc-mode-transitionsThe merged runner stops at the first crossgen2 failure, so no test in
HardwareIntrinsics_General_rorHardwareIntrinsics_General_roruns under R2R. The assemblies compiled before this one (NotSupported_r,ScalarConstantFoldings,SimdConstantFoldings,TestLibrary) succeeded. It is not yet known whether the remainingVector*assemblies compile.Both runners pass in the browser-wasm interpreter leg.
A core dump (
core.1000.300) is uploaded to theHardwareIntrinsics_General_rwork item.Local investigation
Reproduced locally with a browser-wasm Checked build (osx-arm64 host crossgen2). With
Vector128_1_*excluded, crossgen2 next fails onVector128_r.dll. On macOS it does not abort; several JIT worker threads spin at the same place:lower.cpp:5661is thereturn LowerStoreLocCommon(lclStore);afterSpillStructCallResult, on the path for a struct call result that has a single return register and can't be retyped to a primitive. The fault there is re-dispatched over and over. On Linux Helix the same fault shows up as the exit-134 abort above.Because more than one assembly in the runner is affected, the quarantine turns off ReadyToRun for the
HardwareIntrinsics_General_r/_rorunners on wasm CoreCLR. Their interpreter coverage is kept.Configuration
R2R_CG2(crossgen2 at Helix time), Linux x64 hostruntime-coreclr outerloopon [wasm][CoreCLR] Add browser_wasm R2R_CG2 leg to runtime-coreclr outerloop #134960: build 1618213, Helix job470668a9-1c32-41f9-ac2c-a8a0ddd812c3, work itemsHardwareIntrinsics_General_randHardwareIntrinsics_General_roNote
This issue was drafted with GitHub Copilot assistance.