Using the new FSM component for FSM generation

[KelvinChung2000]

The current implementation can compile FSMs without using the compile-static option. A single FSM manages all the control flow.

An example call will be as follows:
./target/debug/calyx -p all -d papercut -d compile-static -d tdcc -b verilog ./test.futil --nested

Thanks to the FSM construct, both onehot-encoded and binary-encoded FSM can be generated.

See here for details.

[rachitnigam]

What's the relationship between this and #2395?

[KelvinChung2000]

This is my implementation of using the new FSM to emit the static FSM. I have also improved the quality of the generated FSM by eliminating potentially unnecessary guarding.

#2395 still requires the static-compile and tdcc, but this implementation can generate Verilog without them.

The fixed in #2395 is not included here.

If @parthsarkar17 is happy with my changes, I think we can merge this into the explicit-fsm-compilation since it is not merging to main anyway. Another option would be to merge #2395 to the explicit-fsm-compilation first, then merge this once all the verification and polishing are completed, and then release everything to main.

If necessary, I am happy to have a meeting to talk about how we should move forward.

[rachitnigam]

Sure! Why don't you grab a slot from the Calyx project page and let us know on the Zulip channel: https://github.com/calyxir/project

[rachitnigam]

Hey @KelvinChung2000! Any updates on the meeting? I can try to make the normal 4pm ET slot work if that's the only one that works for you.