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[TIR] Encode conditional accesses info into block read/write regions#9880

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Hzfengsy merged 2 commits into
apache:mainfrom
wrongtest-intellif:encode_conditional_accesses_in_read_write_annotations
Jan 15, 2022
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[TIR] Encode conditional accesses info into block read/write regions#9880
Hzfengsy merged 2 commits into
apache:mainfrom
wrongtest-intellif:encode_conditional_accesses_in_read_write_annotations

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@wrongtest-intellif

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When we analysis block read/write regions, there are constraints on iter vars not defined within block body. These vars should not be relaxed, but do affect the actual accessed regions.

for i in range(16):
  with T.block():
      if i < 8: 
        # access X[i]

Current analysis will ignore the constraint i < 8 (i is free when analyzing on the block's scope), and get the read region T.reads([X[i:i+1]). This would be an overly relaxed region. If the block nodes are designed to isolate the inner behaviors, the conditional access info will get lost in the read/write annotations.

The pr make a trial to keep awareness also on the free iter vars out of relaxed domain in BlockReadWriteDetector. The result region is intersected with itself relaxed on the domain of free vars. For the case above, it would be [i, i+1) ^ [0, 8), thus if i >= 8, the read region of X becomes empty.

@wrongtest-intellif wrongtest-intellif force-pushed the encode_conditional_accesses_in_read_write_annotations branch from ca62f3b to 0bc0b2a Compare January 8, 2022 18:29
@junrushao

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CC: @spectrometerHBH @Hzfengsy

@Hzfengsy Hzfengsy left a comment

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LGTM.

with T.block():
T.reads(
B[
T.max(i - 2, 0) : T.min(i + -2, 15) + 1,

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Should be T.min(i - 2, 15)?

@Hzfengsy Hzfengsy merged commit 6f6fc68 into apache:main Jan 15, 2022
junrushao added a commit that referenced this pull request Jan 18, 2022
crazydemo pushed a commit to crazydemo/tvm that referenced this pull request Jan 27, 2022
…pache#9880)

* encode conditional accesses info into block read/write regions

* compare ir after simplify
wrongtest-intellif added a commit to wrongtest-intellif/incubator-tvm that referenced this pull request Jan 30, 2022
wrongtest-intellif added a commit to wrongtest-intellif/incubator-tvm that referenced this pull request Feb 8, 2022
Hzfengsy pushed a commit that referenced this pull request Feb 9, 2022
…and support floordiv pattern (#9527)

* allow generate block predicate in compute_at schedule

* revert #9880 and add more testcases
ylc pushed a commit to ylc/tvm that referenced this pull request Feb 16, 2022
…pache#9880)

* encode conditional accesses info into block read/write regions

* compare ir after simplify
ylc pushed a commit to ylc/tvm that referenced this pull request Feb 16, 2022
…and support floordiv pattern (apache#9527)

* allow generate block predicate in compute_at schedule

* revert apache#9880 and add more testcases
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3 participants