Skip to content

risc-v/up_testset: Implement test-and-set with AMOSWAP #14857

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
anchao merged 1 commit into from
Nov 20, 2024
Merged

risc-v/up_testset: Implement test-and-set with AMOSWAP #14857

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
29 changes: 11 additions & 18 deletions arch/risc-v/include/spinlock.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,10 +72,12 @@
*
* RISC-V architecture (in the standard atomic-instruction extension "A")
* supports exclusive accesses to memory locations in the form of the
* Load-Reserved (LR) and Store-Conditional (SC) instructions. RV64 supports
* doubleword aligned data only but others supports word aligned data.
* Load-Reserved (LR), Store-Conditional (SC) and Atomic Memory Operations
* (AMO) instructions. For LR and SC, RV64 supports doubleword aligned data
* only but others supports word aligned data. For AMO, word and doubleword
* alignments are accepted.
*
* RISC-V architecture supports fence instruction to ensure memory ordering
* RISC-V architecture supports fence instruction to ensure memory ordering.
*/

typedef uintptr_t spinlock_t;
Expand Down Expand Up @@ -107,27 +109,18 @@ typedef uintptr_t spinlock_t;
#if defined(CONFIG_ARCH_RV_ISA_A)
static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
{
spinlock_t ret = SP_UNLOCKED;
spinlock_t ret = SP_LOCKED;

__asm__ __volatile__
(
"1: \n"
#ifdef CONFIG_ARCH_RV32
"lr.w %0, (%2) \n"
"amoswap.w %0, %0, %1\n"
#else
"lr.d %0, (%2) \n"
"amoswap.d %0, %0, %1\n"
#endif
"beq %0, %1, 2f \n"
#ifdef CONFIG_ARCH_RV32
"sc.w %0, %1, (%2) \n"
#else
"sc.d %0, %1, (%2) \n"
#endif
"bnez %0, 1b \n"
"fence \n"
"2: \n"
: "+r" (ret)
: "r" (SP_LOCKED), "r" (lock)
"fence\n"
: "+r" (ret), "+A" (*lock)
:
: "memory"
);

Expand Down