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amd64: Add AVX-512 support - #384
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The VEX amd64 guest state now (pyvex feat/avx512) carries 32 512-bit ZMM registers and 8 opmask registers in place of the 16 YMM registers. - Replace the 16 ymmN Register entries with 32 zmmN entries; the old xmmN/xmmNlq/xmmNhq/ymmNhx sub-names are preserved (angr indexes registers by these names) and ymmN/zmmNhy sub-names added. - Add k0..k7. Their offsets resolve from the per-register OFFSET_amd64_K0..K7 defines the updated genoffsets emits. - Extend dwarf_registers with xmm16-31 (DWARF 67-82) and k0-k7 (DWARF 118-125) per the SysV psABI. - fp_ret_offset is unchanged: zmm0 starts where ymm0 did. - New tests pin every amd64 register to a real pyvex guest offset. Arch.__init__ silently gives synthetic offsets to registers whose names don't resolve, so a VEX-side rename would otherwise produce quietly wrong offsets everywhere.
This was referenced Sep 8, 2026
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Corpus decompilation diffs can be found at angr/dec-snapshots@master...angr/archinfo_384 |
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Sync: angr/angr#7120
Sync: angr/pyvex#584