Workspaces README

This repository contains multiple main workspaces:

C.ws

• Contains C language source files and projects.
• Useful for C development, learning, and experimentation.
• Example subfolders:
  • Basic_C_Programs/: Foundational C programs for beginners and learning.
  • DMA_TwoDArrays/: Examples showing Dynamic Memory Allocation of 2D arrays.
  • File_Struct/: Sample code for file handling and structure operations in C.
  • OneD_String/: Programs related to 1D string manipulation in C.
  • Pointer_PreProc_Recursion/: Demonstrations of pointers, preprocessing, and recursion concepts.

Cpp.ws

• Contains C++ language source files and projects.
• Useful for C++ development, learning, and experimentation.
• Example subfolders:
  • Assignments/: Contains various C++ assignments.
  • BasicClasses/: Examples demonstrating basic class concepts.
  • BasicsCPP/: Foundational C++ programs and tutorials.
  • InheritanceClasses/: Examples showcasing inheritance in C++.
  • Namespaces_FileHandling/: Demonstrations of namespaces and file handling.
  • OperatorOverload/: Examples of operator overloading.
  • PracticeQuestion/: Practice questions and exercises.
  • StringsAnd1DArray/: C++ code for string and 1D array manipulation.

Verilog.ws

• Contains Verilog hardware description language modules, projects, and workspace files.
• Useful for digital design, simulation, and hardware experimentation.
• Example subfolders:
  • LED_Peripheral/: Example modules and logic for LED control peripherals.
  • LED_ROM/: Sample ROM components or LED ROM interface designs.
  • Switch_Level_Models/ : Switch Level Models for basic modules
  • Light_Controller/: Verilog modules for light/LED controller logic and testbenches.
  • Synchronous_FIFO/: FIFO buffer implementations and associated testbenches.

Getting Started

1. Clone the repository.
2. Explore the C.ws, Cpp.ws, and Verilog.ws directories for code samples and projects.
3. Follow any instructions in individual project folders to build and run the code, or use a suitable simulator for Verilog.

Contributing

Feel free to contribute by adding new projects or improving existing ones in any workspace.

License

See individual files or projects for license information.