Upstream update available: designs/src/liteeth/dev/repo

[claude]

Upstream update available: designs/src/liteeth/dev/repo

Field	Value
Pinned	0eca508 (2025-05-26)
Upstream	6a6791b (2026-04-28)
Commits behind	86
Days stale	337

Severity: MAJOR

The diff contains substantial RTL changes: a redesigned CRC engine (16-bit support removed, new checking engine added), new protocol stacks (PTP IEEE 1588v2 slave, IGMP Multicast), and two new version releases (2025.08 and 2025.12). These changes affect the RTL that HighTide synthesizes.

What changed

• CRC engine redesign: 16-bit CRC support removed; new dedicated CRC check engine added — direct RTL change
• New IGMP Multicast Group Joiner: new module integrated into LiteEthIPCore / LiteEthUDPIPCore
• New PTP Slave Core (IEEE 1588v2, Layer 3): new hardware module with bench and test utilities
• Configurable MTU for jumbo frame support; configurable UDP port CDC FIFO depth
• Bug fix: Stream2UDPTX packet truncation on mid-packet disable
• SRAM improvements: simplified logic and naming in mac/sram; VOGL-electronic SRAM PR merged
• PHY additions: Altera Agilex3/5 RGMII PHY, USRGMII IO delay configuration
• Wishbone interface fix: LiteEthMACWishboneInterface mode set correctly
• Test suite: migrated to pytest; all tests updated and cleaned up
• Version bumps: 2025.08 and 2025.12 releases
• Efinix RGMII improvements: Titanium/Trion RGMII refactored, RMII rx_er support

Recommendation

Update with care. The CRC engine redesign and new IGMP/PTP modules are RTL-affecting; after updating, re-run synthesis on all six liteeth variants to confirm no regressions. The 2025.12 release date suggests this is a stable snapshot worth tracking. The Stream2UDPTX packet-truncation fix may change post-synthesis behaviour on stream variants.

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Last refreshed: 2026-05-04T09:41:35Z