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Correct CSRRW State Change #364

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Merged
dANW34V3R merged 3 commits into from
Dec 20, 2023
Merged

Correct CSRRW State Change #364

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1e6597d
Only update state when needed and remove unused variable
dANW34V3R Dec 18, 2023
19d7d15
Remove unsued variable
dANW34V3R Dec 18, 2023
b66e62b
Clang format
dANW34V3R Dec 19, 2023
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15 changes: 13 additions & 2 deletions src/lib/arch/riscv/ExceptionHandler.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -649,13 +649,18 @@ bool ExceptionHandler::init() {
auto operands = instruction_.getSourceOperands();
auto destinationRegs = instruction_.getDestinationRegisters();

uint8_t rm = 0b110; // Set to invalid rounding mode
uint64_t result = 0;

ProcessStateChange stateChange;
switch (instruction_.getMetadata().opcode) {
case Opcode::RISCV_CSRRW: // CSRRW rd,csr,rs1
if (metadata.operands[1].reg == RISCV_SYSREG_FRM) {
// Update CPP rounding mode but not floating point CSR as currently no
// implementation

rm = operands[0].get<uint64_t>() & 0b111; // Take the lower 3 bits

switch (operands[0].get<uint64_t>()) {
case 0: // RNE, Round to nearest, ties to even
fesetround(FE_TONEAREST);
Expand Down Expand Up @@ -688,10 +693,16 @@ bool ExceptionHandler::init() {
// implementation of Zicsr
break;
}
// Shift rounding mode to correct position, frm[5:7]
result = rm << 5;
}

// Dummy logic to allow progression. Set Rd to 0
stateChange = {ChangeType::REPLACEMENT, {destinationRegs[0]}, {0ull}};
// Only update if registers should be written to
if (destinationRegs.size() > 0) {
// Dummy logic to allow progression. Set Rd to 0
stateChange = {
ChangeType::REPLACEMENT, {destinationRegs[0]}, {result}};
}
break;
default:
printException(instruction_);
Expand Down
2 changes: 0 additions & 2 deletions src/lib/arch/riscv/Instruction_execute.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1149,7 +1149,6 @@ void Instruction::execute() {
// the sign of zero, although some implementations additionally enforce
// that if one argument is +0 and the other is -0, then +0 is returned.
// But RISC-V spec requires this to be the case
double res;
if (rs1 == 0 && rs2 == 0) {
results[0] = RegisterValue(0x0000000000000000, 8);
} else {
Expand All @@ -1162,7 +1161,6 @@ void Instruction::execute() {
const float rs2 = checkNanBox(operands[1]);

// Comments regarding fmaxf similar to RISCV_FMAX_D
float res;
if (rs1 == 0 && rs2 == 0) {
results[0] = RegisterValue(0xffffffff00000000, 8);
} else {
Expand Down