Further AArch64 coverage targeting the CloverLeaf benchmark#199
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Further AArch64 coverage targeting the CloverLeaf benchmark#199
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… instruction with tests.
…f Vector Length becomes more than 512-bit.
…struction with tests.
…certain SVE instructions that calculates NZCV reg values based on predicate result.
… instruction with tests.
…edicate)) with tests.
…. Also fixed float version of this instruction to preserve inactive elements in the destination vector.
…ction with tests.
…ruction with tests.
jj16791
approved these changes
Nov 12, 2021
Contributor
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#rerun tests |
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Further coverage of the AArch64 ISA has been made to add support for the following CloverLeaf versions :
Both benchamrks have been supported and tested using the TX2, armv8.4-a, and armv8.4-a+sve architecture targets on SimEng.
The majority of these commits have been for the ArmClang compiled versions of CloverLeaf_* targeting armv8.4-a+sve, with some helper functions also being created in areas where the same code was being repeatedly used.
The final commit
a1e3a5baddresses an uncommon issue where specific length binary names (inc. their path) would push necessary null pointers off the top of the stack, resulting in a data abort error.