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[GOLD-RING] fix(compiler): restore declarations dropped by batch merge #1783 — master does not compile - #1788

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fix/repair-verilog-codegen-merge
Aug 6, 2026
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gHashTag merged 2 commits into
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fix/repair-verilog-codegen-merge

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@gHashTag gHashTag commented Aug 6, 2026

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Closes #1787

master does not compile. cargo build --release in bootstrap/ fails with 27 errors. Every contributor is blocked. This PR restores compilation.

What happened

PR #1783 (batch-merge-wave-loops-w420-w459) resolved its conflicts by keeping the wave-loop call sites while dropping the declarations they depend on.

The failure was masked: build.rs panics on the stale FROZEN_HASH seal (also not updated by #1783) before rustc runs, so the build stops at a seal error and the real compile errors never surface. Resealing exposes them.

What this restores

Every item was recovered from its originating commit — none of it was reconstructed by hand.

Item From Was
6 VerilogCodegen fields + initializers in all 3 constructors WL458 E0609 × 12
type_is_float, gen_verilog_let_destructuring, tuple_element_widths, is_simple_tuple_type WL455/458 E0599
let type_array = Self::parse_array_type(..) at both consumer sites WL455 E0425
base/idx bindings + W383 local-array flattening block WL458 E0425
json_out plumbing (SuiteOptions field + --json CLI arg) WL440 E0425
HashSet import, fast → opts.fast — E0433/E0425

One adaptation rather than a straight revert: WL455's parse_array_type returned Option<(usize, String)>, master's returns Option<(Vec<usize>, String)> (multi-dimensional — the newer, better API). The consumers are adapted to master's signature by folding the dims into a flat element count, rather than reverting the API.

Two silent behaviour losses also fixed

  • parse_let_destructuring routed let (a, b) = expr to a StmtAssign + ExprArrayLiteral{extra_kind="tuple"} shape that only the Verilog backend reads. Rust/C/Zig read the older StmtLocal + extra_field shape, so Rust emitted vec![s, d] = dm(a, b); — uncompilable. Routed back through parse_local_decl, whose shape all four backends already lower.
  • parse_type_annotation joined tuple elements with , instead of the canonical , , so -> (u32, u32) became -> (u32,u32).

Result

before after
cargo build --release 27 errors 0 errors
unit tests could not run 1528 / 1535 pass

FROZEN_HASH resealed (M5), per FROZEN.md §5.

Still red — needs the wave-loop authors

Seven tests remain failing. They are feature-level losses from the same merge, all in Verilog hardware lowering:

tests_w457_ram_style::ram_style_block_pragma_emitted
tests_w457_ram_style::ram_style_distributed_pragma_emitted
tests_w458::array_param_read_emitted
tests_w458::no_translate_off_comments
tests_w458::tests_w459::array_param_bound_from_test_block
tests_w458::tests_w459::test_block_emits_real_function_call
tests_hir_pipeline_parity::test_verilog_keyword_local_and_module_escaped

I deliberately did not reconstruct these. Guessing at RTL lowering semantics produces output that looks plausible and synthesizes wrong — strictly worse than a visibly failing test. Leads are in #1787: for ram_style the pragma never reaches the module-level var declaration though every other piece survives; for array_param the binding is written and read but the parameter is never rewritten to the bound module array.

These seven fail on master today too — they simply could not be observed, because nothing compiled.

🤖 Generated with Claude Code

master did not compile: PR #1783 (batch-merge-wave-loops-w420-w459)
kept the wave-loop call sites while dropping the declarations they
depend on. The stale FROZEN_HASH seal masked it -- build.rs panics
before rustc runs, so 27 real compile errors never surfaced.

Restored from their originating commits rather than reconstructed:

  - 6 VerilogCodegen fields + initializers in all 3 constructors
  - type_is_float, gen_verilog_let_destructuring,
    tuple_element_widths, is_simple_tuple_type
  - the two 'let type_array = parse_array_type(..)' bindings, adapted
    to master's newer multi-dimensional Option<(Vec<usize>, String)>
    API by folding the dims into a flat element count
  - base/idx bindings + the W383 local-array flattening block
  - suite.rs/main.rs: json_out plumbing (WL440), HashSet import,
    fast -> opts.fast

Two silent behaviour losses also fixed: 'let (a, b) = expr' was routed
to a StmtAssign+ExprArrayLiteral shape only the Verilog backend reads,
so Rust emitted 'vec![s, d] = dm(a, b);'; and parse_type_annotation
joined tuple elements with ',' instead of the canonical ', '.

master compiles again; 1528/1535 unit tests pass. Seven remain red --
Verilog lowering features lost by the same merge, left for their
authors rather than guessed at.

FROZEN_HASH resealed (M5).

Closes #1787

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@gHashTag gHashTag added this to the EPOCH-01-HARDEN milestone Aug 6, 2026
Only docs/NOW.md conflicted (both sides prepend entries); all entries kept.
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📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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PR Dashboard

Generated at: 2026-08-06 12:15:33 UTC

Summary

Status Count
Total Open PRs 3
PRs with Failing Checks 1
PRs with All Checks Green 2
READY 1
FAILING 1
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=66ce0d11508e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag merged commit 493a7a0 into master Aug 6, 2026
23 checks passed
gHashTag added a commit that referenced this pull request Aug 6, 2026
… + master diagnosis

specs/ternary/gft_dot8.t27: a spec-first GF-T16 8-term dot product
(realistic inference / attention-head tile length), balanced reduction
tree. Verified: typecheck 0 err; in-spec test (8.0 = 22016); iverilog
cross-check vs the same tree from silicon-proven gft_dot2+gft_add =
ALL_PASS on 2000 random inputs (bit-exact). GF-T ladder: dot2->dot4->dot8.

NOW.md documents a master codegen diagnosis: current master is red (7
internal tests + yosys broken) from #1783 batch-merge drops that #1788
only partially repaired. The tests-section emits `// synthesis
translate_off` but closes with `endif (unbalanced -> breaks yosys);
one-line fix = emit `ifndef SIMULATION (verified). 6 other red tests are
distinct dropped features. Not pushed (multi-bug repair + reseal sweep
in an active-repair area = owner decision). The spec-first hardware
delta applies + builds clean on master and lands once those go green.

Refs #1764

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@gHashTag
gHashTag deleted the fix/repair-verilog-codegen-merge branch October 26, 2026 04:52
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master does not compile: batch merge #1783 (w420-w459) dropped declarations while keeping their call sites

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