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test(gen-verilog): guard nested-if/else reg-decl hoist (#1741) - #1751
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The existing #1741 regression test covered only the while-loop shape. Add a second case reproducing GF-T's gft_mul_offset_full_p: a second same-block local declared after a leading statement (carry; carry=...; sum;) plus a local inside an else branch (result). On the pre-fix emitter this emitted a reg declaration after a procedural statement, which iverilog -g2012 rejects. Asserts all locals are hoisted before the first statement, none re-declared mid-block, and the output elaborates under Icarus Verilog. Also refreshes docs/NOW.md. Refs #1697 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-08-06 08:43:12 UTC
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Summary
Adds a regression test for the
gen-verilogfunction-localreghoist, covering the nestedif/elseshape that the existing test (while_loop_with_locals_lowers_and_elaborates) did not exercise.The emitter fix itself already landed in
mastervia #1741 (fix(gen-verilog): hoist function-local reg decls to body top). This PR is test-only (plus adocs/NOW.mdentry) — it locks in the exact scenario that motivated #1741 so it cannot silently regress.Refs #1697 (harden the codegen backend / conformance).
What the new test does
nested_if_else_locals_lower_and_elaboratereproduces thegft_mul_offset_full_pshape:carry; carry = ...; sum;)elsebranch (result)It asserts:
carry,sum,result) are declared before the first statement inbegin : mul_offset_body,iverilog -g2012(skips gracefully when iverilog is absent).Verified that this test fails against the pre-#1741 emitter (interleaved
reg [31:0] sum;→ iverilog exit 2) and passes on currentmaster.Test
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