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ci(fpga-build): place-and-route the AX7203 WASM top to a .bit artifact (Closes #12456) - #12624

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gHashTag merged 7 commits into
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Oct 26, 2026
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gHashTag merged 7 commits into
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Closes #12456 (milestone B, part B2). See #12387 (the DOOM on the AX7203 dashboard), #9367 (the WASM tracker) and Trinity-S-AI-DNA/trinity-fpga#917.

What changes

The job fpga-synth-ax7203 of .github/workflows/fpga-build.yml no longer stops at the cell receipt. When fpga/verilog/wasm_board_ax7203_top.v exists (hashFiles gate, the same path gate as before), it continues:

  1. chipdb xc7a200tfbg484-2.bin: restored from the Actions cache (actions/cache/restore@v5, fixed key chipdb-xc7a200tfbg484-2-regymm-openxc7-v1), md5 checked against the pinned 59f828c441e6e6081bfee63ff994660e; on a miss or a wrong md5 it is generated from prjxray-db inside regymm/openxc7 (bbaexport.py then bbasm -l, the .bba deleted) and saved right after generation (actions/cache/save@v5), so a later failure of the same run does not lose it. A freshly generated chipdb whose md5 differs from the pin only warns.
  2. XDC: gf16_clean_ax7203.xdc of gHashTag/trinity-fpga at commit ad15ec5f56bb53a0fb29e9d74e6e5f6f62092886 (rst_n T6, led B13 C13 D14 D15, uart_rx P20, uart_tx N15), fetched with bounded retries; it must be 714 bytes.
  3. yosys synth_xilinx -flatten -abc9 -arch xc7 -top wasm_board_ax7203_top over the generated cell plus the board top, then setundef -zero -params and write_json, as the proven gf16 bitstream recipe of trinity-fpga does.
  4. nextpnr-xilinx seeds 1 to 16 (--placer sa --router router1 --freq 50.0 --timing-allow-fail, 3600 s each) until one routes; the winning log is nextpnr.log.
  5. fasm2frames and xc7frames2bit; the exit of xc7frames2bit is the verdict.
  6. receipt.txt gains the seed, chipdb md5, XDC sha256, ZINV_T1 lines and tristate pad lines (informational, the ZINV_T1 trap of the archived nextpnr-xilinx), the nextpnr utilisation lines and the .bit size. The artifact is renamed wasm-board-ax7203 and carries wasm_board_ax7203.bit, the FASM, both yosys logs, nextpnr.log and receipt.txt.
  7. timeout-minutes 90 to 300.

Budget and gates

  • fpga-build.yml: +36 -5 lines (budget 40), under the label owner-approved-foreign given for fpga-build: AX7203 board top for the WASM cell (STARTUPE2 clock, UART and LED pins) and place-and-route to a bitstream #12456.
  • Paid by deleting two dead files: fpga/vivado/matmul_serial_io.v (31 lines) and fpga/diagnostics/decode_matmul_serial.py (88 lines); neither is referenced outside .md files, neither is in the foreign exceptions.
  • Censuses: shell run steps 336 to 340, quiet shapes 35 to 37, re-blessed in their own commit naming the numbers; fetches did not move. The one new "ABSENT" line in quiet is the census reading the volume spec of the chipdb step as a path, not a missing file.
  • lefthook pre-commit (foreign-budget, own-language, secret-gate) and tri census pin --gate pass on every commit; actionlint -shellcheck= is clean.

What is and is not measured

Nothing of this was run: the first CI run of this PR is the first place-and-route of the WASM cell for the AX7203. Expected unknowns the run will answer: whether a seed routes, the utilisation of the top, the .bit size, and how long the chipdb generation takes on a cold cache. No number is claimed before the run prints it.

The coverage check may be red here as it is on master since be3e0d141e (a stale crons_t27os-night-loop.json seal); the fix is #12599, not this PR.

Frames

This PR changes no RTL, so run 3 of the video core renders from the same cell binary as run 2: the title frame passes hg_check (verdict 0) and the pattern frame is written. They are shown in the session, not attached here.

Bench

A board load of the .bit waits for the owner's explicit yes (openFPGALoader -c digilent_hs2 --busdev-num 0:4, SRAM only, never -f); until that receipt exists, every "run" is a simulation.

🤖 Generated with Claude Code

gHashTag and others added 3 commits October 26, 2026 10:43
Closes #12456)

The job fpga-synth-ax7203 now continues after the cell receipt, when
fpga/verilog/wasm_board_ax7203_top.v exists (hashFiles gate):

- chipdb for xc7a200tfbg484-2: restored from the Actions cache (fixed key
  naming the part and the image), md5 checked against the pinned
  59f828c441e6e6081bfee63ff994660e, regenerated from prjxray-db inside
  regymm/openxc7 on a miss or a wrong md5, and saved right after generation
  (cache/save, so a later failure does not lose it).
- the pinned XDC of trinity-fpga commit ad15ec5f56 is fetched with bounded
  retries and must be 714 bytes.
- yosys synth_xilinx of the cell plus the board top (with -DSIMULATION as
  the cell step has it), then nextpnr-xilinx over seeds 1 to 16 until one
  routes, then fasm2frames and xc7frames2bit (its exit is the verdict).
- receipt.txt gains the seed, chipdb md5, XDC sha256, ZINV_T1 and tristate
  pad line counts, nextpnr utilisation lines and the .bit size; the artifact
  is renamed wasm-board-ax7203 and carries wasm_board_ax7203.bit.
- timeout-minutes 90 -> 300.

Foreign budget: +36 -5 lines in fpga-build.yml, paid by deleting the dead
fpga/vivado/matmul_serial_io.v (31 lines, no reference, no port) and
fpga/diagnostics/decode_matmul_serial.py (88 lines, no reference). Nothing
was run or measured yet: the first run of the PR is the first measurement.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…2 steps of #12456 (Refs #12456)

The place-and-route steps added to fpga-synth-ax7203 in the previous commit
moved two pinned censuses; fetches did not move.

- shell: run: steps 336 -> 340 (the runner does 315 -> 319): four new
  bash steps (chipdb and XDC, yosys of the top, nextpnr seed search,
  fasm2frames plus receipt).
- quiet: steps in a quiet shape 35 -> 37, named a path but not quiet
  264 -> 271, gated on the file existing 10 -> 12: the new steps are gated on
  hashFiles of the board top, which exists in this tree, so nothing guards
  nothing. The one new "ABSENT" line (fpga-build.yml:674 PWD:/work) is the
  census reading the docker volume spec "$PWD:/work" of the chipdb step as a
  path; it is not a missing file.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…s the proven AX7203 recipe does (Refs #12456)

The gf16 bitstream workflow of gHashTag/trinity-fpga, the one recipe that
has produced a working .bit for this part with regymm/openxc7, runs
setundef -zero -params before write_json so that no parameter bit reaches
nextpnr-xilinx undefined. The board-top synthesis step takes the same
line; the cell-only receipt step is unchanged. One line edited, no new
line.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-26 04:19:12 UTC

Summary

Status Count
Total Open PRs 21
PRs with Failing Checks 19
PRs with All Checks Green 2
READY 0
FAILING 19
PENDING 0
NO CHECKS YET 1

These columns do not partition: 0 + 19 + 0 + 1 = 20, and there are 21 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=8ddf64a0178e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@tri-claw

tri-claw Bot commented Oct 26, 2026 •

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Summary by t27-bees

The PR extends the fpga-synth-ax7203 job to perform full place-and-route and bitstream generation for the AX7203 WASM top when fpga/verilog/wasm_board_ax7203_top.v exists. It adds chipdb caching with md5 pinning, XDC fetching with sha256 verification, a second yosys synthesis pass for the board top, nextpnr-xilinx with seeds 1–4, and fasm2frames/xc7frames2bit to produce the .bit artifact. Two dead files are removed to stay within the line budget.

Worth a look

  • .github/workflows/fpga-build.yml:674 (chipdb step) — The docker run --memory 14g limit exceeds the 7 GB RAM of GitHub ubuntu-latest runners; the container can attempt to allocate more than the host has, risking OOM kills. The same applies to the 12g limits in the yosys/nextpnr steps.
  • .github/workflows/fpga-build.yml:688–689 (chipdb md5 check) — A regenerated chipdb whose md5 differs from the pinned 59f828c441e6e6081bfee63ff994660e only emits a warning and continues; a silently corrupted or incompatible chipdb would not fail the build.
  • .github/workflows/fpga-build.yml:693–695 (XDC fetch) — The XDC is fetched from a raw GitHub URL with retries, but a transient network failure or upstream repo change (the commit is pinned but the raw URL could become unavailable) would fail the job with no local fallback.
  • .github/workflows/fpga-build.yml:710–724 (nextpnr seed loop) — Only seeds 1–4 are tried (the description mentions 1–16); if none route, the job fails. The per-seed timeout is 2400 s (40 min), so four seeds consume up to 160 min of the 300 min job timeout, leaving limited margin for the bitstream steps.
  • .github/workflows/fpga-build.yml:655–660 (FF/MEM awk parser) — The new awk script splits reg declarations into flip-flop bits and memory bits based on unpacked dimensions; complex Verilog (e.g., multi-dimensional arrays, parameterized widths, or packed/unpacked mixes) could be miscounted, causing false budget passes or failures.

Read: 5 files, +50 -139, the whole diff. Head f4106fe. Model: openai-compatible/nvidia/nemotron-3-ultra-550b-a55b. Commands: @t27-bees review | summary | help | pause | resume. Free for every repository.

gHashTag and others added 2 commits October 26, 2026 12:22
…db save after regeneration, XDC sha256 pin, 4 seeds x 2400 s (Refs #12456)

Register-bit budget: the BRAM lowering of #12364 keeps the memory page as `reg [7:0] NAME[0:65535];`, so a text count over `reg` cannot tell a memory from flip-flops and charged 524288 memory bits against the 269200 flip-flops. The gate now counts flip-flop bits (no unpacked dimension) and memory bits (with one) apart, fails above 269200 and above 13455360 (365 RAMB36E1 x 36864), and the synthesis receipt proves the inference: it sums the RAMB36E1 + RAMB18E1 and FDRE + FDCE + FDPE + FDSE cells from the yosys stat and fails when memory is declared but no RAMB cell exists.
tri-claw[bot] review of #12624: the chipdb cache is saved again after an md5 mismatch regenerated it (id chipdb, regen output); the pinned XDC is checked by sha256 instead of by size; the nextpnr loop is 4 seeds x 2400 s, so two yosys runs of 60 min plus 4 x 40 min is 280 min inside timeout-minutes 300 (it was 16 x 3600 s).
Lines: 2 pairs of lines folded into one line each pay the 2 new lines (foreign budget, net zero).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…build.yml receipt gate (Refs #12456)

The new fpga-synth-ax7203 line that reads and appends to build/fpga/ax7203/receipt.txt (awk over the receipt, tee -a) adds two commands that name a path and print, so the count moves by two; the one listed entry moves from fpga-build.yml:674 to :675 because of the new `id: chipdb` line. No group is new; only tools/census/quiet.txt changes.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…nder the per-file cap (Refs #12456)

The pre-push foreign-budget gate counts added lines of a file against
origin/master, not against the last pushed head: the receipt-gate rewrite
of five pre-existing lines took the file from 36 to 41 added lines. Two
lines of the same step become one; the text is unchanged.

Census: the quiet reading "PWD:/work" at fpga-build.yml:675 is now at line 674
(the joined line above it is gone); the quiet count stays 273. Re-blessed here.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-26 05:40:54 UTC

Summary

Status Count
Total Open PRs 22
PRs with Failing Checks 20
PRs with All Checks Green 2
READY 0
FAILING 20
PENDING 0
NO CHECKS YET 1

These columns do not partition: 0 + 20 + 0 + 1 = 21, and there are 22 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=6fb540d220f7 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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Run 1 of this PR (head ce0397c) was red on fpga-synth-ax7203, cli-tri and coverage. Head f4106fe answers the first two and the three "Worth a look" points of the review summary; coverage is master's own red (a stale crons_t27os-night-loop seal, #12599) and is not touched here.

Why the synth job was red: the budget gate, not the cell. The register-bit step multiplied every [a:b] of every reg declaration, so the 64 KiB memory page (reg [7:0] NAME[0:65535]) counted as 524288 flip-flop bits and the gate stopped the job at 536154 > 269200 before yosys ran. The page is BRAM-shaped since #12364 (specs/compiler/verilog_bram_shape.t27, which closed #12297 and is in this branch's base). Now the step counts packed dimensions before the name as flip-flop bits (cap 269200) and unpacked dimensions after the name as memory bits (cap 13455360, the 365 RAMB36E1 of the xc7a200t), prints both, and the receipt after synth_xilinx proves the inference instead of guessing it: RAMB36E1 + RAMB18E1 >= 1 whenever memory bits are declared, and FDRE + FDCE + FDPE + FDSE <= 269200. On the pre-page cell of #12457's receipt (5717 bits, run 40256973572) the new split gives 2637 flip-flop bits + 3080 memory bits; the page's run is this PR's.

Review point 1, chipdb saved after a regeneration. The chipdb step has id: chipdb and sets regen=true when the md5 did not match and the file was rebuilt; the actions/cache/save condition is now cache-hit != 'true' || regen == 'true'. Honest limit: a GitHub cache entry is immutable under its key, so a save after a regeneration under the same -v1 key is expected to warn rather than overwrite. Bumping the key is the follow-up if a regeneration is ever observed; the md5 warning on the next run would show it.

Review point 2, the XDC pinned by content. The 714-byte size check is replaced by the sha256 7256eb2516f4ae90d83d1527dd88b9866df70e5dc554775d714ec17667e7d378 of the pinned trinity-fpga constraints file at ad15ec5f.

Review point 3, the seed loop against the job timeout. Seeds 1 to 4 with timeout --signal=KILL 2400 each (was 16 x 3600). Worst case: two yosys runs of up to 60 min plus 4 x 40 min = 280 min, under the job's timeout-minutes: 300.

cli-tri. The first red was master's own census move (#12625, fetches 50 -> 49), gone after the master merge; the yml edits then moved quiet 271 -> 273 and the reading at line 675 to 674, each re-blessed in its own commit naming the number.

Nothing of this has run on the board: the .bit, its size and the LUT/FF/RAMB numbers come from this PR's own run, and the flash receipt is a separate step on the owner's word.

🤖 Addressed by Claude Code

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The coverage red on this head is master's own, not this PR's. The job Every seal still describes its spec fails on master itself (Seal Coverage runs 40271326185 on 833925fe47 and 40273324519 on 2283ad50c8) with eleven seals that newly do not hold: ten [stale] (cli_git_commands, crons_t27os-night-loop, git_commands, t27b_T27bWasm, t27f_T27fWorkGraph, t27f_a11y_mirror, t27f_hud, t27os_T27osHiveFeedAcceptance, t27os_T27osLabLegs, t27os_labs) and queen_local_dispatch as [gen-drift]. This PR touches none of those specs or seals. The refresh is #12626 (seals/corpus-refresh); no second fix is filed here. Nothing is pushed for this red: a reviewer can discount coverage while master's own run of the job fails, and this branch takes a clean merge of master once the refresh lands.

🤖 Addressed by Claude Code

@gHashTag
gHashTag merged commit 2389c8f into master Oct 26, 2026
38 of 40 checks passed
@gHashTag
gHashTag deleted the lane/wasm-b2-pnr-12456 branch October 26, 2026 14:30
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doom-ax7203 DOOM on the AX7203: every issue of the WASM board route (epic #12387) owner-approved-foreign Owner-approved exception to the only-t27 rule: hand-written foreign code allowed in this PR

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fpga-build: AX7203 board top for the WASM cell (STARTUPE2 clock, UART and LED pins) and place-and-route to a bitstream

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