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ci(fpga-build): place-and-route the AX7203 WASM top to a .bit artifact (Closes #12456) - #12624
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Closes #12456) The job fpga-synth-ax7203 now continues after the cell receipt, when fpga/verilog/wasm_board_ax7203_top.v exists (hashFiles gate): - chipdb for xc7a200tfbg484-2: restored from the Actions cache (fixed key naming the part and the image), md5 checked against the pinned 59f828c441e6e6081bfee63ff994660e, regenerated from prjxray-db inside regymm/openxc7 on a miss or a wrong md5, and saved right after generation (cache/save, so a later failure does not lose it). - the pinned XDC of trinity-fpga commit ad15ec5f56 is fetched with bounded retries and must be 714 bytes. - yosys synth_xilinx of the cell plus the board top (with -DSIMULATION as the cell step has it), then nextpnr-xilinx over seeds 1 to 16 until one routes, then fasm2frames and xc7frames2bit (its exit is the verdict). - receipt.txt gains the seed, chipdb md5, XDC sha256, ZINV_T1 and tristate pad line counts, nextpnr utilisation lines and the .bit size; the artifact is renamed wasm-board-ax7203 and carries wasm_board_ax7203.bit. - timeout-minutes 90 -> 300. Foreign budget: +36 -5 lines in fpga-build.yml, paid by deleting the dead fpga/vivado/matmul_serial_io.v (31 lines, no reference, no port) and fpga/diagnostics/decode_matmul_serial.py (88 lines, no reference). Nothing was run or measured yet: the first run of the PR is the first measurement. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…2 steps of #12456 (Refs #12456) The place-and-route steps added to fpga-synth-ax7203 in the previous commit moved two pinned censuses; fetches did not move. - shell: run: steps 336 -> 340 (the runner does 315 -> 319): four new bash steps (chipdb and XDC, yosys of the top, nextpnr seed search, fasm2frames plus receipt). - quiet: steps in a quiet shape 35 -> 37, named a path but not quiet 264 -> 271, gated on the file existing 10 -> 12: the new steps are gated on hashFiles of the board top, which exists in this tree, so nothing guards nothing. The one new "ABSENT" line (fpga-build.yml:674 PWD:/work) is the census reading the docker volume spec "$PWD:/work" of the chipdb step as a path; it is not a missing file. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…s the proven AX7203 recipe does (Refs #12456) The gf16 bitstream workflow of gHashTag/trinity-fpga, the one recipe that has produced a working .bit for this part with regymm/openxc7, runs setundef -zero -params before write_json so that no parameter bit reaches nextpnr-xilinx undefined. The board-top synthesis step takes the same line; the cell-only receipt step is unchanged. One line edited, no new line. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Summary by t27-beesThe PR extends the Worth a look
Read: 5 files, +50 -139, the whole diff. Head |
…db save after regeneration, XDC sha256 pin, 4 seeds x 2400 s (Refs #12456) Register-bit budget: the BRAM lowering of #12364 keeps the memory page as `reg [7:0] NAME[0:65535];`, so a text count over `reg` cannot tell a memory from flip-flops and charged 524288 memory bits against the 269200 flip-flops. The gate now counts flip-flop bits (no unpacked dimension) and memory bits (with one) apart, fails above 269200 and above 13455360 (365 RAMB36E1 x 36864), and the synthesis receipt proves the inference: it sums the RAMB36E1 + RAMB18E1 and FDRE + FDCE + FDPE + FDSE cells from the yosys stat and fails when memory is declared but no RAMB cell exists. tri-claw[bot] review of #12624: the chipdb cache is saved again after an md5 mismatch regenerated it (id chipdb, regen output); the pinned XDC is checked by sha256 instead of by size; the nextpnr loop is 4 seeds x 2400 s, so two yosys runs of 60 min plus 4 x 40 min is 280 min inside timeout-minutes 300 (it was 16 x 3600 s). Lines: 2 pairs of lines folded into one line each pay the 2 new lines (foreign budget, net zero). Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…build.yml receipt gate (Refs #12456) The new fpga-synth-ax7203 line that reads and appends to build/fpga/ax7203/receipt.txt (awk over the receipt, tee -a) adds two commands that name a path and print, so the count moves by two; the one listed entry moves from fpga-build.yml:674 to :675 because of the new `id: chipdb` line. No group is new; only tools/census/quiet.txt changes. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
…nder the per-file cap (Refs #12456) The pre-push foreign-budget gate counts added lines of a file against origin/master, not against the last pushed head: the receipt-gate rewrite of five pre-existing lines took the file from 36 to 41 added lines. Two lines of the same step become one; the text is unchanged. Census: the quiet reading "PWD:/work" at fpga-build.yml:675 is now at line 674 (the joined line above it is gone); the quiet count stays 273. Re-blessed here. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
PR DashboardGenerated at: 2026-10-26 05:40:54 UTC
Summary
Seal Status
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Run 1 of this PR (head ce0397c) was red on Why the synth job was red: the budget gate, not the cell. The register-bit step multiplied every Review point 1, chipdb saved after a regeneration. The chipdb step has Review point 2, the XDC pinned by content. The 714-byte size check is replaced by the sha256 Review point 3, the seed loop against the job timeout. Seeds 1 to 4 with cli-tri. The first red was master's own census move (#12625, fetches 50 -> 49), gone after the master merge; the yml edits then moved Nothing of this has run on the board: the 🤖 Addressed by Claude Code |
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The 🤖 Addressed by Claude Code |
Closes #12456 (milestone B, part B2). See #12387 (the DOOM on the AX7203 dashboard), #9367 (the WASM tracker) and Trinity-S-AI-DNA/trinity-fpga#917.
What changes
The job
fpga-synth-ax7203of.github/workflows/fpga-build.ymlno longer stops at the cell receipt. Whenfpga/verilog/wasm_board_ax7203_top.vexists (hashFilesgate, the same path gate as before), it continues:xc7a200tfbg484-2.bin: restored from the Actions cache (actions/cache/restore@v5, fixed keychipdb-xc7a200tfbg484-2-regymm-openxc7-v1), md5 checked against the pinned59f828c441e6e6081bfee63ff994660e; on a miss or a wrong md5 it is generated from prjxray-db insideregymm/openxc7(bbaexport.pythenbbasm -l, the.bbadeleted) and saved right after generation (actions/cache/save@v5), so a later failure of the same run does not lose it. A freshly generated chipdb whose md5 differs from the pin only warns.gf16_clean_ax7203.xdcof gHashTag/trinity-fpga at commitad15ec5f56bb53a0fb29e9d74e6e5f6f62092886(rst_n T6, led B13 C13 D14 D15, uart_rx P20, uart_tx N15), fetched with bounded retries; it must be 714 bytes.synth_xilinx -flatten -abc9 -arch xc7 -top wasm_board_ax7203_topover the generated cell plus the board top, thensetundef -zero -paramsandwrite_json, as the proven gf16 bitstream recipe of trinity-fpga does.--placer sa --router router1 --freq 50.0 --timing-allow-fail, 3600 s each) until one routes; the winning log isnextpnr.log.xc7frames2bitis the verdict.ZINV_T1 linesandtristate pad lines(informational, the ZINV_T1 trap of the archived nextpnr-xilinx), the nextpnr utilisation lines and the.bitsize. The artifact is renamedwasm-board-ax7203and carrieswasm_board_ax7203.bit, the FASM, both yosys logs,nextpnr.logandreceipt.txt.timeout-minutes90 to 300.Budget and gates
fpga-build.yml: +36 -5 lines (budget 40), under the labelowner-approved-foreigngiven for fpga-build: AX7203 board top for the WASM cell (STARTUPE2 clock, UART and LED pins) and place-and-route to a bitstream #12456.fpga/vivado/matmul_serial_io.v(31 lines) andfpga/diagnostics/decode_matmul_serial.py(88 lines); neither is referenced outside.mdfiles, neither is in the foreign exceptions.shellrun steps 336 to 340,quietshapes 35 to 37, re-blessed in their own commit naming the numbers;fetchesdid not move. The one new "ABSENT" line inquietis the census reading the volume spec of the chipdb step as a path, not a missing file.tri census pin --gatepass on every commit;actionlint -shellcheck=is clean.What is and is not measured
Nothing of this was run: the first CI run of this PR is the first place-and-route of the WASM cell for the AX7203. Expected unknowns the run will answer: whether a seed routes, the utilisation of the top, the
.bitsize, and how long the chipdb generation takes on a cold cache. No number is claimed before the run prints it.The
coveragecheck may be red here as it is on master sincebe3e0d141e(a stalecrons_t27os-night-loop.jsonseal); the fix is #12599, not this PR.Frames
This PR changes no RTL, so run 3 of the video core renders from the same cell binary as run 2: the title frame passes
hg_check(verdict 0) and the pattern frame is written. They are shown in the session, not attached here.Bench
A board load of the
.bitwaits for the owner's explicit yes (openFPGALoader -c digilent_hs2 --busdev-num 0:4, SRAM only, never-f); until that receipt exists, every "run" is a simulation.🤖 Generated with Claude Code