Repository navigation
fix(codegen): iverilog-clean gen-verilog + BPSK modem spec - #1250
Merged
Merged
Conversation
Port of the gen-verilog/parser fixes to master so datapath specs compile & simulate: (1) parse_const_decl consumes trailing ';' -> consecutive const/var runs no longer dropped (uart 1->8 localparams, 31->0 iverilog errors); (2) integer literals render as decimal (0x/0b/_ -> valid Verilog); (3) guarded early return rewritten to if/else; (4) struct-field regs named by the holding var; (5) zero-arg functions get a dummy input; (6) function bodies use named begin blocks. Existing ExprCast handling kept. New specs/fpga/bpsk.t27 (ZeroDSP_BPSK, trios-mesh BPSK modem core) iverilog- compiles AND simulates: 13 embedded test assertions pass; correlate(Barker)=13, inversion=-13, sidelobes -5/+5, sync gate, frame=21. uart/mac clean too. Closes #1245 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Contributor
|
📓 NotebookLM Notebook linked to this PR
This notebook contains session context, decisions, and artifacts for this work. |
Contributor
This was referenced Jul 1, 2026
gHashTag
added a commit
that referenced
this pull request
Jul 2, 2026
#1255) Reseal every spec so suite seal-verify is green after the gen-verilog change (#1250) shifted gen-hashes for most specs; also clears pre-existing spec-hash drift + missing seals. Three spec pairs shared a module name and collided on their <dir>_<Module>.json seal (FeedForward, String, malformed "[]const u8") -> rename the second of each pair (FeedForwardNetwork / SacredGovernance / FacultyBoard). Suite: parse/typecheck/gen(x4)/seal-verify 514/514. Closes #1254 Co-authored-by: gHashTag <deborahnelson8788726@gmail.com> Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
This was referenced Jul 2, 2026
This was referenced Aug 21, 2026
gHashTag
added a commit
that referenced
this pull request
Aug 27, 2026
* gen-c, gen: a module-level `var` is mutable (Refs #2161) The parser records mutability in `extra_mutable`, and both backends already branch on it for function LOCALS -- Zig `var` vs `const`, Rust `let mut` vs `let`. The module-level paths never read it, so a `var` at module scope was emitted as a constant: gen-c #define counter 0 -> `counter = counter + 1` becomes `0 = (0 + 1)`, which is not C gen const counter: u32 -> Zig refuses the assignment gen-verilog reg [31:0] counter correct all along gen-c now emits `static <type> <name> = <init>;` for a mutable module-level declaration and keeps `#define` / `static const` for real constants. Zig writes `var` instead of `const`. Measured over the 42 specs whose C output this changes: C compile errors (cc -fsyntax-only -std=c11) 537 -> 277 specs whose generated C is clean 0 -> 19 specs/fpga/bpsk.t27 -- the BPSK modem merged in #1250 -- goes 7 errors to 0. A probe spec compiles and RUNS: two calls to a function that increments a module-level counter print `1 2`. Immutable constants are untouched: `const K: u32 = 7` still emits `#define K 7`. gen-rust is NOT fixed here, and the reason is a language question rather than an oversight. Rust has no safe module-level mutable: `static mut` needs `unsafe` at every access, `AtomicU32` changes the access API to load/store, and `thread_local!` changes the semantics. All three alter the generated interface, so which one t27 means belongs to whoever owns the datapath. Measured first: all 43 of these specs already produce Rust that does not compile, for reasons beyond this one, so nothing regresses by leaving it. Parse count unchanged at 620/746; t27c tests unchanged at 1629 passed / 6 failed. FROZEN_HASH resealed in the same commit (M5). * docs/now: a module-level var was a constant in three backends (Refs #2161)
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Closes #1245. Makes
t27c gen-verilogemit iverilog-compilable, simulatable RTL for datapath specs, and adds the trios-mesh BPSK modem core asspecs/fpga/bpsk.t27.Backend fixes (
bootstrap/src/compiler.rs)parse_const_declnow consumes the trailing;(a stray;made the module-body loop skip subsequent decls). uart: 1 -> 8 localparams, 31 -> 0 iverilog errors.0x/0b/_integer literals render as decimal (valid Verilog).if/elseso the return is not clobbered (last-write-wins).varname (matches field access).input(Verilog forbids port-less functions).Existing
ExprCastcast handling kept as-is (master's validated version).New
specs/fpga/bpsk.t27(ZeroDSP_BPSK)BPSK serializer + Barker-13 preamble + integer correlator + threshold sync. iverilog-compiles AND simulates: 13 embedded test assertions pass; hierarchical checks give correlate(Barker)=13, inversion=-13, sidelobes -5/+5, sync gate, frame=21. uart/mac now iverilog-clean too (fpga clean 1 -> 3 of 34).
Validation
suite: parse / typecheck / gen(Zig/Rust/Verilog/C) 514/514.phi^2 + phi^-2 = 3 | TRINITY