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seals: reseal StorageKv, stale since today's merges (Closes #12347) - #12386
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specs/storage/kv.t27's four gen hashes moved under it (rust, zig, c and verilog together -- a generator-side move, not a spec edit: the seal's spec_hash still matches). check_seal_currency goes red for every open PR on it; this records what the compiler now produces, the #12348 pattern. Both twins (StorageKv.json, storage_StorageKv.json) refreshed; coverage 3058 seals, 0 newly broken; currency 0 stale on the tree's own compiler.
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Summary by t27-beesThis PR reseals the StorageKv module by updating all four generator hashes (C, Rust, Verilog, Zig), the seal timestamp, and the spec hash. It also empties the dependency closure in Worth a look
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…, Refs #9367) Merging nine more commits of origin/master conflicted in one seal file, analog_AnalogMosTable. It took master's version and was re-sealed with the cast-widening emitter, so only gen_hash_verilog (plus built_by and sealed_at) differs from master. tri seals drift lists nothing else of mine. The remaining stale pair, StorageKv and storage_StorageKv, comes from master: specs/storage/kv.t27 changed there after it was sealed (fix: #12386), and this branch touches neither file. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Brings in the StorageKv reseal (#12386) so the coverage seal check passes on this branch. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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… (Refs #12419) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…sion (Closes #12296) (#12338) * fix(gen-verilog): a cast to a wider integer widens the Verilog expression (Closes #12296) The ExprCast arm of gen_verilog_expr printed the operand of `x as u64` verbatim. Verilog sizes an expression to its widest operand, so `(a as u64) + (b as u64) > (lim as u64)` over u32 inputs stayed a 32-bit add and wrapped, while the interpreter (test-report runs zig) computed it at 64 bits: t27c test-report said 42 of 42 and vvp failed mem_access_past_the_page_traps on the WASM cell. A cast to a wider integer target now emits an explicit extension: zero-extending `{{(W-N){1'b0}}, op}` for an unsigned operand, sign-extending `{{(W-N){($signed(op) < 0)}}, op}` for a signed one, wrapped in `$signed(...)` for a signed target. The enclosing expression is then sized by the cast target, so sums and comparisons run at the widened width. Literal, unknown-width, float and 32-bit-plus signed-composite operands keep their old forms. Also: unit tests test_verilog_cast_width_correct (adds the u32 -> u64 sum and an i32 -> i64 case), test_verilog_cast_no_as_keyword and accepts_valid_cast_as_control follow the new text; the corpus spec specs/fpga/w5_cast_widen.t27 with its icarus baseline is the regression witness; tools/elab_baseline.txt gains the row `w5_cast_widen 0` (the ratchet reads specs/fpga by directory); bootstrap/stage0/FROZEN_HASH moves with compiler.rs. Refs #9367 Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): FROZEN_HASH regenerated for the merged compiler.rs (Refs #12296, Refs #9367) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(census): re-bless for t27os.yml, which arrived on master with the ledgers un-moved (Refs #12296, Refs #11788) The census moved because #12330 added .github/workflows/t27os.yml on master and did not re-bless: workflow files read 67 -> 68, jobs 96 -> 97, run: steps 329 -> 331, runner-named shells 308 -> 310. Written by tri census pin --bless, checked by tri census pin --gate (rc 0). Data only, no code. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal 235 seal files whose Verilog moved with the cast-widening fix (Refs #12296, Refs #9367) The emitter now extends a cast to a wider integer explicitly, so the Verilog of 220 specs (235 seal files with their twins) changed. In every one of them gen_hash_verilog is the only generated hash that moved; gen_hash_zig, gen_hash_rust and gen_hash_c are unchanged. The re-seal also refreshes built_by and, where it had gone stale, the test_runner hash. Written by tri seals drift --fix plus t27c seal specs/t27f/face.t27 --save (that one aborts in a build with overflow checks, array_size - 1 at compiler.rs:15134 on master, so the binary was built with CARGO_PROFILE_DEV_OVERFLOW_CHECKS=false, which matches the release build). The four stale seals that master already carries (GitDiff, git_GitDiff, TriBuilder, pipeline_TriBuilder: specs/git/diff.t27 and specs/tri/pipeline/builder.t27 changed after sealing) are left alone; #12348 and #12350 own them. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal the three specs whose Verilog moved after merging master (Refs #12296, Refs #9367) Merging origin/master (27 commits) conflicted in three seal files: fpga_wasm_opcodes, t27f_a11y_mirror and t27os_T27osAgentParts. Each took master's version and was re-sealed with the cast-widening emitter, so only gen_hash_verilog (plus built_by and sealed_at) differs from master. Six seals that my earlier re-seal had written against the older spec (JitSemantics, PackedVsa, TriBuilder and their twins) are restored to master's versions: master moved those specs and re-sealed them, and its seals already match the emitter output. tri seals drift: 0 specs moved. check_seal_coverage: OK, no gen-drift and no stale. check_seal_currency: 0 stale. tri census pin --gate: PASS. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal analog raw_writer and sar_switch after merging master (Refs #12296, Refs #9367) Merging ten more commits of origin/master conflicted in two seal files, analog_AnalogRawWriter and analog_AnalogSarSwitch. Each took master's version and was re-sealed with the cast-widening emitter, so only gen_hash_verilog (plus built_by and sealed_at) differs from master. tri seals drift lists nothing else of mine. The remaining stale pair, StorageKv and storage_StorageKv, comes from master: specs/storage/kv.t27 changed there after it was sealed, and this branch touches neither file. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal analog mos_table after merging master (Refs #12296, Refs #9367) Merging nine more commits of origin/master conflicted in one seal file, analog_AnalogMosTable. It took master's version and was re-sealed with the cast-widening emitter, so only gen_hash_verilog (plus built_by and sealed_at) differs from master. tri seals drift lists nothing else of mine. The remaining stale pair, StorageKv and storage_StorageKv, comes from master: specs/storage/kv.t27 changed there after it was sealed (fix: #12386), and this branch touches neither file. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal t27f frame_render after merging master (Refs #12296, Refs #9367) Merging b1a5857 of origin/master conflicted in one seal file, t27f_frame_render. It took master's version and was re-sealed with the cast-widening emitter, so only gen_hash_verilog (plus built_by and sealed_at) differs from master. tri seals drift listed nothing else. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal t27os provider_profile after merging master (Refs #12296, Refs #9367) Master's b1a5857 brought in the provider_profile spec with a seal made by the master emitter. Its gen_hash_verilog moves with the cast-widening emitter, so it was re-sealed; only gen_hash_verilog (plus built_by and sealed_at) differs from master. The FpgaHdmiGrab seal is left alone: it was sealed on 2026-10-20 and its spec_hash no longer matches hdmi_grab.t27 on master itself, which this branch does not touch. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal four specs after merging master (Refs #12296, Refs #9367) Merging origin/master into the branch conflicted in three seal files (analog_AnalogSarComparator, analog_AnalogSarComparatorQ, t27os_T27osAgentParts). The master versions were taken and the specs re-sealed with the cast-widening emitter. tri seals drift also listed t27os/hot_reload, whose only moved hash is gen_hash_verilog. Against master only gen_hash_verilog (plus built_by and sealed_at, and the nested import spec_hash of sar_comparator_q and agent_parts) differs. The doctor, glass_window, lab_publish, pty_server and receipt_name seals moved in every hash, so they are master's stale seals and are left alone. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal analog sar_comparator after the second master merge (Refs #12296, Refs #9367) Master's 0fd2a8c changed specs/analog/sar_comparator.t27 and re-sealed it. The merge kept this branch's older seal; master's file was restored and re-sealed with the cast-widening emitter. Against master only gen_hash_verilog (plus built_by and sealed_at) differs, and tri seals drift lists nothing else. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * merge: resolve seal artefacts and FROZEN_HASH to master's version * chore(seal): re-freeze compiler.rs and re-seal three wasm specs after merging master (Refs #12296, Refs #9367) Merging origin/master (853a782, with the BRAM-shape emitter change of #12297) conflicted in bootstrap/stage0/FROZEN_HASH and in the seals of fpga/wasm_board_ax7203, fpga/wasm_opcodes and tri/t27b/wasm. The merged compiler.rs hash is recorded in FROZEN_HASH again, and the three seals were taken from master and re-saved with the merged emitter. Against master only gen_hash_verilog (plus built_by and sealed_at) differs in those seals, and tri seals drift lists nothing else. compiler.rs is still 40 added / 40 deleted against master. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal t27f spec_graph_fold and spec_graph_view after merging master (Refs #12296, Refs #9367) The branch on the remote had taken two master merges while this branch was being fixed. After integrating both, tri seals drift lists four specs. Two of them (t27f/spec_graph_fold and t27f/spec_graph_view) moved only in gen_hash_verilog, which is the cast-widening emitter, and are re-sealed here. The other two (crons/t27os-night-loop and t27os/hive_feed_acceptance) moved in every hash including spec_hash, so they are master's stale seals and are left alone. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal four specs after merging master (Refs #12296, Refs #9367) Merging origin/master (8384eb9) conflicted only in four t27os seals. Earlier merges on this branch had kept stale copies of twelve files that master had since rewritten (wasm_board_ax7203, wasm_opcodes, the fpga verilog and workflow files, the night-loop spec, the census ledgers). This merge takes master's side, so the PR differs from master again only in compiler.rs, its frozen hash, w5_cast_widen and the seals. tri seals drift then lists six specs. Four moved only in gen_hash_verilog, which is the cast-widening emitter, and are re-sealed here: fpga/wasm_board_ax7203, fpga/wasm_opcodes, t27os/release, t27os/statusbar. The other two (crons/t27os-night-loop and t27os/hive_feed_acceptance) moved in every hash including spec_hash, so they are master's stale seals and are left alone. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal claw merge_judge and pr_tools after merging master (Refs #12296, Refs #9367) Master (6b9fa51) re-sealed claw/merge_judge and claw/pr_tools. Both moved only in gen_hash_verilog under this branch's cast-widening emitter, so they are re-sealed here. tri seals drift now lists only crons/t27os-night-loop and t27os/hive_feed_acceptance, which are master's stale seals (every hash moved, including spec_hash) and are left alone. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> * chore(seal): re-seal t27f scene after merging master (Refs #12296, Refs #9367) Merging origin/master (9a6e4e7) was clean with -X theirs. The PR differs from master only in compiler.rs, its frozen hash, w5_cast_widen and the seals. tri seals drift lists eight specs: specs/t27f/scene moved only in gen_hash_verilog (the cast-widening emitter) and is re-sealed here. The other seven (crons/t27os-night-loop, t27f/a11y_mirror, t27f/hud, t27f/work_graph, t27os/hive_feed_acceptance, t27os/lab_legs, tri/t27b/wasm) moved in spec_hash too, so master's spec changed without a re-seal; they are master's stale seals and are left alone. compiler.rs is still 40 added / 40 deleted against master and matches bootstrap/stage0/FROZEN_HASH. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> --------- Co-authored-by: Claude Sonnet 5.5 <noreply@anthropic.com>
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The gate's own repair, the #12348 pattern: specs/storage/kv.t27's four gen hashes (rust, zig, c, verilog) moved under their seal, so check_seal_currency (the spec-guards step) is red for every PR open against master right now -- verified red on pristine master at 15acb60 before this.
Refs #12347.